CS47L85 datasheet(174/370 Pages) CIRRUS

174 / 370 page

CS47L85

174

Rev 4.3

AIF MASTER / SLAVE CONTROL

The digital audio interfaces can operate in Master or Slave modes and also in mixed master/slave configurations. In Master

mode, the BCLK and LRCLK signals are generated by the CS47L85 when any of the respective digital audio interface

channels is enabled. In Slave mode, these outputs are disabled by default to allow another device to drive these pins.

Master mode is selected on the AIFnBCLK pin using the AIFn_BCLK_MSTR register bit. In Master mode, the AIFnBCLK

signal is generated by the CS47L85 when one or more AIFn channels is enabled.

When the AIFn_BCLK_FRC bit is set in BCLK master mode, the AIFnBCLK signal is output at all times, including when

none of the AIFn channels is enabled. The AIFn_BCLK_FRC bit should be held at 0 if SYSCLK is not enabled. SYSCLK

must be present and enabled before setting the AIFn_BCLK_FRC bit. See “Clocking and Sample Rates” for further details

(including requirements for reconfiguring SYSCLK while AIF clock signals are enabled).

The AIFnBCLK signal can be inverted in Master or Slave modes using the AIFn_BCLK_INV register.

Master mode is selected on the AIFnLRCLK pin using the AIFn_LRCLK_MSTR register bit. In Master mode, the AIFnLRCLK

signal is generated by the CS47L85 when one or more AIFn channels is enabled.

When the AIFn_LRCLK_FRC bit is set in LRCLK master mode, the AIFnLRCLK signal is output at all times, including when

none of the AIFn channels is enabled. Note that AIFnLRCLK is derived from AIFnBCLK, and an internal or external

AIFnBCLK signal must be present to generate AIFnLRCLK. The AIFn_LRCLK_FRC bit should be held at 0 if SYSCLK is

not enabled. SYSCLK must be present and enabled before setting the AIFn_LRCLK_FRC bit. See “Clocking and Sample

Rates

” for further details (including requirements for reconfiguring SYSCLK while AIF clock signals are enabled).

The AIFnLRCLK signal can be inverted in Master or Slave modes using the AIFn_LRCLK_INV register.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1280

(0500h)

AIF1_BCL

K_Ctrl

AIF1_BCLK_INV

AIF1 Audio Interface BCLK Invert

0 = AIF1BCLK not inverted

1 = AIF1BCLK inverted

This bit is locked when AIF1 channels are

enabled; it can only be changed when all

AIF1 channels are disabled.

AIF1_BCLK_FRC

AIF1 Audio Interface BCLK Output Control

0 = Normal

1 = AIF1BCLK always enabled in Master

mode

AIF1_BCLK_MST

AIF1 Audio Interface BCLK Master Select

0 = AIF1BCLK Slave mode

1 = AIF1BCLK Master mode

This bit is locked when AIF1 channels are

enabled; it can only be changed when all

AIF1 channels are disabled.

R1282

(0502h)

AIF1_Rx_

Pin_Ctrl

AIF1_LRCLK_IN

AIF1 Audio Interface LRCLK Invert

0 = AIF1LRCLK not inverted

1 = AIF1LRCLK inverted

This bit is locked when AIF1 channels are

enabled; it can only be changed when all

AIF1 channels are disabled.

AIF1_LRCLK_FR

AIF1 Audio Interface LRCLK Output

Control

0 = Normal

1 = AIF1LRCLK always enabled in Master

mode

AIF1_LRCLK_MS

AIF1 Audio Interface LRCLK Master

Select

0 = AIF1LRCLK Slave mode

1 = AIF1LRCLK Master mode

This bit is locked when AIF1 channels are

enabled; it can only be changed when all

AIF1 channels are disabled.

Table 37 AIF1 Master / Slave Control

CS47L85 Datasheet(PDF) 174 Page - Cirrus Logic

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