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AM2634 Datasheet(PDF) 1 Page - Texas Instruments |
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AM2634 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 164 page  AM263x Sitara™ Microcontrollers 1 Features Processor Cores: • Single, dual, and quad-core Arm® Cortex®-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-core capable clusters Memory Subsystem: • 2MB of On-Chip RAM (OCSRAM) – 4 Banks x 512KB – ECC error protection – Internal DMA engine support System on Chip (SoC) Services and Architecture: • 1x EDMA to support data movement functions • Device Boot supported from the following interfaces: – UART (Primary/Backup) – QSPI NOR Flash (4S/1S) (Primary) • Interprocessor communication modules – SPINLOCK module for synchronizing processes running on multiple cores – MAILBOX functionality implemented through CTRLMMR registers • Central Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routers Media and Data Storage: • 1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface • General-Purpose Memory Controller (GPMC) – 16-bit parallel data bus with 22-bit address bus – Up to 4MB addressable memory space – Integrated Error Location Module (ELM) support for error checking General Connectivity: • 6x Universal Asynchronous RX-TX (UART) • 5x Serial Peripheral Interface (SPI) controllers • 5x Local Interconnect Network (LIN) ports • 4x Inter-Integrated Circuit (I2C) ports • 4x Modular Controller Area Network (MCAN) modules with CAN-FD support • 1x Quad Serial Peripheral Interface (QSPI) • 4x Fast Serial Interface Transmitters (FSITX) • 4x Fast Serial Interface Receivers (FSIRX) • Up to 140 General-Purpose I/O (GPIO) pins Sensing & Actuation: • Real-time Control Subsystem (CONTROLSS) • Flexible Input/Output Crossbars (XBAR) • 5x 12-bit Analog-to-Digital Converters (ADC) – 6-input SAR ADC up to 4 MSPS • 6x Single-ended channels OR • 3x Differential channels – Highly Configurable ADC Digital Logic • XBAR Start of Conversion Triggers (SOC) • User-defined Sample and Hold (S+H) • Flexible Post-Processing Blocks (PPB) • 10x Analog Comparators with Type-A programmable DAC reference (CMPSSA) • 10x Analog Comparators with Type-B programmable DAC reference (CMPSSB) • 1x 12-bit Digital-to-Analog Converter (DAC) • 32x Pulse Width Modulation (EPWM) modules – Single or Dual PWM channels – Advanced PWM Configurations – Extended HRPWM time resolution • 10x Enhanced Capture (ECAP) modules • 3x Enhanced Quadrature Encoder Pulse (EQEP) modules • 2x 4-Ch Sigma-Delta Filter Modules (SDFM) • Additional Signal-multiplex Crossbars (XBAR) Industrial Connectivity: • Programmable Real-Time Unit (PRU-SS) and PRU-Industrial Communication Subsystem (PRU- ICSS) – Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1) • Deterministic Hardware • Dynamic Firmware – 20-channel enhanced input (eGPI) per PRU – 20-channel enhanced output (eGPO) per PRU – Embedded Peripherals and Memory • 1x UART, 1x ECAP • 1x MDIO, 1x IEP, • 1x 32KB Shared General Purpose RAM • 2x 8KB Shared Data RAM • 1x 12KB IRAM per PRU • ScratchPad (SPAD), MAC/CRC – Digital encoder and sigma-delta control loops – The PRU-ICSS enables advanced industrial protocols including: • EtherCAT®, Ethernet/IP™, • PROFINET®, IO-Link® for order – Dedicated Interrupt Controller (INTC) – Dynamic CONTROLSS XBAR Integration AM2634, AM2634-Q1, AM2632, AM2632-Q1, AM2631, AM2631-Q1 SPRSP74C – OCTOBER 2022 – REVISED NOVEMBER 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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