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– Case GpmcFCLKDivider = 1:

– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime

are even)

– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise

– Case GpmcFCLKDivider = 2:

– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3)

– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)

– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)

(10) For WE falling edge (WE activated):

– Case GpmcFCLKDivider = 0:

– I = 0.5 × WEExtraDelay × GPMC_FCLK(17)

– Case GpmcFCLKDivider = 1:

– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime

are even)

– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise

– Case GpmcFCLKDivider = 2:

– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3)

– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)

– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):

– Case GpmcFCLKDivider = 0:

– I = 0.5 × WEExtraDelay × GPMC_FCLK (17)

– Case GpmcFCLKDivider = 1:

– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime

are even)

– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise

– Case GpmcFCLKDivider = 2:

– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3)

– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)

– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)

(11) J = GPMC_FCLK(17)

(12) First transfer only for CLK DIV 1 mode.

(13) Half cycle; for all data after initial transfer for CLK DIV 1 mode.

(14) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.

(15) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.

(16) P = GPMC_CLK period in ns

(17) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

(18) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(19) 100MHz GPMC_FCLK selected - CTRLMMR_GPMC_CLKSEL[0] CLK_SEL = 1 = MAIN_PLL2_HSDIV7_CLKOUT (100/60 MHz)

(20) In div_by_1_mode, GPMC0_CLK refers to either GPMC0_CLKOUT or GPMC0_FCLK_MUX (free-running). Both signals are pin-

muxed to the same pin

– GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

– GPMC0_CLK frequency = GPMC_FCLK frequency

In not_div_by_1_mode, GPMC0_CLK only refers to GPMC0_CLKOUT. GPMC0_FCLK_MUX cannot be clock divided to match the

GPMC0_CLKOUT frequency if GPMCFCLKDIVIDER > 0

– GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:

– GPMC0_CLK frequency = GPMC_FCLK frequency / (2 to 4)

AM2634, AM2634-Q1, AM2632, AM2632-Q1, AM2631, AM2631-Q1

SPRSP74C – OCTOBER 2022 – REVISED NOVEMBER 2022

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