S12ECT16B8CV2 datasheet(136/152 Pages) NXP

136 / 152 page

MC9S12XDP512 Device User Guide — V01.12

The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,

typical values are 50.

ζ = 0.9 ensures a good transient response.

And finally the frequency relationship is defined as

With the above values the resistance can be calculated. The example is shown for a loop bandwidth

fC=43kHz:

The capacitance Cs can now be calculated as:

The capacitance Cp should be chosen in the range of:

A.5.3.2 Jitter Information

The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the

deviation from the reference clock fref is measured and input voltage to the VCO is adjusted

accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.

Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock

jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.

ζ f

ref

⋅⋅

πζ





⋅

------------------------------------------

------

ref

410

⋅

--------------

ζ 0.9

()

;

→

fC < 100kHz

VCO

ref

-------------

synr

()

⋅

= 20

π nf

⋅⋅ ⋅

KΦ

-----------------------------

π 20 43kHz

⋅⋅

⋅

539.1Hz

() Ω

⁄

--------------------------------------------

10.0k

Ω

⋅

π f

C R

⋅⋅

----------------------

0.516

C R

⋅

---------------

ζ 0.9

()

;

= 1.2nF = ~ 1.0nF

-------

≤≤

CP = 100pF

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

S12ECT16B8CV2 Datasheet(PDF) 136 Page - NXP Semiconductors

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