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S12ECT16B8CV2 Datasheet(PDF) 104 Page - NXP Semiconductors |
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S12ECT16B8CV2 Datasheet(HTML) 104 Page - NXP Semiconductors |
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104 / 152 page ![]() MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12 • Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. • VSSPLL must be directly connected to VSSR. • Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8 and Q1 as small as possible. • Do not place other signals or supplies underneath area occupied by C7, C8 and Q1 and the connection area to the MCU. • Central power input should be fed in at the VDDA/VSSA pins. Table 28-1 Recommended decoupling capacitor choice Component Purpose Type Value C1 VDD1 filter cap ceramic X7R 400nF C2 VDD2 filter cap (not 80 QFP) ceramic X7R 400nF C3 VDDA filter cap ceramic X7R 100nF C4 VDDR filter cap X7R/tantalum >=100nF C5 VDDPLL filter cap ceramic X7R 200nF C6 VDDX filter cap X7R/tantalum >=100nF C7 OSC load cap C8 OSC load cap C9 PLL loop filter cap See PLL specification chapter C10 PLL loop filter cap C11 VDDX filter cap X7R/tantalum >=100nF C12 VDDX filter cap X7R/tantalum >=100nF R1 PLL loop filter res See PLL specification chapter Q1 Quartz Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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