AD1986ABSTZ datasheet(31/56 Pages) AD

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AD1986A

Rev. 0 | Page 31 of 56

ADC

ADC Status

VREF_OUT pin output states controlled by the CVREF, MVREF, and LVREF controls in Register 0x70.

REF

VREF Status

Voltage References, VREF and VREF_OUT not ready.

REF (RO)

(Voltage

References, VREF

and VREF_OUT

status (read

only))

Voltage References, VREF, and VREF_OUT up to nominal level.

PR0

All ADCs and input selectors’ power down: clearing this bit enables VREF regardless of the state of PR3.

Default: all ADCs and input muxes powered on (0x0).

PR1

Front DACs power-down. Also powers down the EQ circuitry. Clearing this bit enables VREF regardless of the state of

PR3. Default: all DACs and EQ powered on (0x0).

PR2

Analog mixer power-down. (valid if PR7 = 0).

Default: analog mixer powered on (0x0).

PR3

All VREF and VREF_OUT pins power-down. May be used in combination with PR2 or by itself. If all the ADCs and DACs

are not powered down, setting this bit will have no effect on the VREF and will only power down VREF_OUT.

Default: All VREFand VREF_OUT pins powered on (0x0).

PR4

AC-Link Interface power-down. The reference and the mixer can be either up or down, but all power-up sequences

must be allowed to run to completion before PR5 and PR4 are both set. In multiple-codec systems, the master codec’s

PR4 bit controls the slave codec. In the slave codec the PR4 bit has no effect except to enable or disable PR5.

Default: AC-link Interface powered on (0x0).

PR5

Internal Clocks disabled.

PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down (for example, PR0, PR1, PR4). The reference

and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5

and PR4 are both set. In multiple codec systems, the master codec’s PR5 controls the slave codec. PR5 is effective in the

slave codec if the master's PR5 bit is clear. Default: internal clocks enabled (0x0).

PR6

Powers down the headphone amplifiers.

Default: HP amp powered on (0x0).

EAPD

EAPD Pin Status

Sets the EAPD pin low, enabling an external power amplifier.

Default

EAPD

Sets the EAPD pin high, shutting the external power amplifier off.

Reserved.

Default: 0

EXTENDED AUDIO ID (REGISTER 0x28)

The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates one

or more of the extended audio features are supported.

Reg

Name

D15

D14

D13

D12

D11

D10

Default

0x28

Ext’d Audio ID

ID1

ID0

REV1

REV0

AMAP

LDAC

SDAC

CDAC

DSA1

DSA0

SPDF

DRA

VRA

0x0BC7

Table 90.

Description

Setting

Function

VRA (RO)

Variable rate PCM audio: read only

= 1

Variable rate PCM audio supported

SPDIF (RO)

SPDIF support: read only

= 1

SPDIF transmitter supported (IEC958)

DRA (RO)

Double rate audio: read only

= 1

Double rate audio supported for DAC0 L/R

DSA [1:0]

DAC slot assignment (read/write)

Front DAC

Surround DAC

C/LFE DAC

Default

DSA [1:0]

Left

Right

Left

Right

Left

Right

Default

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