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AD1986ABSTZ Datasheet(PDF) 41 Page - Analog Devices |
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AD1986ABSTZ Datasheet(HTML) 41 Page - Analog Devices |
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41 / 56 page  AD1986A Rev. 0 | Page 41 of 56 REF JS1 JS0 JSMT2 JSMT1 JSMT0 HP OUT LINE OUT C/LFE OUT SURR OUT MONO OUT NOTES 20 OUT (0) OUT (0) 1 0 1 FMUTE FMUTE FMUTE FMUTE ACTIVE JS0 no mute action 21 OUT (0) IN (1) 1 0 1 FMUTE FMUTE FMUTE FMUTE ACTIVE JS1 mutes mono and enables all rear. 22 IN (1) OUT (0) 1 0 1 ACTIVE ACTIVE ACTIVE ACTIVE FMUTE 23 IN (1) IN (1) 1 0 1 ACTIVE ACTIVE ACTIVE ACTIVE FMUTE Standard six channel configuration swapped HP_OUT and LINE_OUT 24 OUT (0) OUT (0) 1 1 0 ** ** ** ** ** **RESERVED 25 OUT (0) IN (1) 1 1 0 ** ** ** ** ** 26 IN (1) OUT (0) 1 1 0 ** ** ** ** ** 27 IN (1) IN (1) 1 1 0 ** ** ** ** ** 28 OUT (0) OUT (0) 1 1 1 ** ** ** ** ** **RESERVED 29 OUT (0) IN (1) 1 1 1 ** ** ** ** ** 30 IN (1) OUT (0) 1 1 1 ** ** ** ** ** 31 IN (1) IN (1) 1 1 1 ** ** ** ** ** FMUTE = Output is forced to mute independent of the respective volume register setting. ACTIVE = Output is not muted and its status is dependent on the respective volume register setting. OUT = Nothing is plugged into the jack and therefore the JS status is 0 (via the load resistor pull-down action). IN = Jack has plug inserted and therefore the JS status is 1 (via the codec JS pin internal pull-up). SERIAL CONFIGURATION (REGISTER 0x74) When Register 0x00 is written (soft reset) the SLOT 16, REGM [2:0], SPOVR, SPAL, SPDZ, and SPLNK bits do not reset. All bits are reset on a hardware reset or power-on reset. Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x74 Serial Configuration SLOT 16 REGM2 REGM1 REGM0 REGM3 OMS2 OMS1 OM0 SPOVR LBKS1 LBKS0 INTS CSWP SPAL SPDZ SP LNK 0x1001 Table 105. Register Function Default This bit enables S/PDIF to link with the front DACs for data requesting. When linked, the S/PDIF and front DACs should be set to the same data rate because they both generate data requests at the front DACs request rate. SPLNK Function 0 S/PDIF and front DACs are not linked SPLNK (S/PDIF LINK) 1 S/PDIF and front DACs are linked Default Sets data fill mode for S/PDIF transmitter FIFO under-runs. When this bit is set to on (1), the S/PDIF and ADC rates should be set to the same rate. SPDZ On Under-Runs 0 Repeat last sample out the S/PDIF stream Default SPDZ (S/PDIF DACZ) 1 Forces midscale sample out the S/PDIF stream SPAL S/PDIF Transmitter Source 0 Connected to the AC-LINK stream Default SPAL (S/PDIF ADC Loop Around) 1 Connected to the digital ADC stream Swaps the center/LFE channels. Some systems have a swapped external connection for the center and LFE channels. Setting this bit will swap these channels internal to the codec. The center and LFE controls do not change and remain at the same addresses and bit assignments. CSWP CENTER Pin LFE Pin 0 Center channel LFE channel Default (CSWP Center/LFE Swap) 1 LFE channel Center channel |
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