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AD1986ABSTZ Datasheet(PDF) 39 Page - Analog Devices |
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AD1986ABSTZ Datasheet(HTML) 39 Page - Analog Devices |
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39 / 56 page  AD1986A Rev. 0 | Page 39 of 56 JACK SENSE (REGISTER 0x72) All register bits are read/write except for JS0ST and JS1ST, which are read only. Important: Refer to Table 103 to understand how JACK_SENSE_A and JACK_SENSE_B codec pins translate to JS1and JS0. Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x72 Jack Sense JS1 SPRD JS1 DMX JS0 DMX JSMT 2 JSMT 1 JSMT 0 JS1 EQB JS0 EQB x x JS1 MD JS0 MD JS1 ST JS0 ST JS1 INT JS0 INT 0x0000 Table 103. Register Function Indicates JS0 has generated an interrupt. Remains set until the software services JS0 interrupt; that is, JS0 ISR should clear this bit by writing a 0 to it. Interrupts are generated by valid state changes of JS pins. Interrupt to the system is actually an OR combination of this bit and JS3 JS0 INT. The interrupt implementation path is selected by the INTS bit (Register 0x74). It is also possible to generate a software system interrupt by writing a 1 to this bit. JS0INT Read Write 0 JS0 did not generate interrupt No operation JS0INT (JS0 Interrupt Status) 1 JS0 generated interrupt Clears JS0INT bit Indicates JS1 has generated an interrupt. Remains set until the software services JS1 interrupt; that is, JS1 ISR should clear this bit by writing a 0 to it. See the JS0INT description above for additional details. JS1INT Read Write 0 JS1 did not generate interrupt No operation JS1INT (JS1 Interrupt Status) 1 JS1 generated interrupt Clears JS1INT This bit always reports the logic state of JS0. On MIC jack sensing, depending on the applications circuit, the logic state for jack sense pins can be the opposite to that on other jacks. Software needs to be aware that this interprets the JS event as a plug in the out event. JS0ST Function Default 0 JS0 is low (0) JS0ST (RO) (JS0 State) 1 JS0 is high (1) This bit always reports the logic state of JS1. MIC jack sensing, depending on the applications circuit, the logic state for JS pins can be the opposite to the other jacks. JS1ST Function 0 JS1 is low (0) JS1ST (RO) (JS1 State) 1 JS is high (1) This bit selects the operation mode for JS0. JS0MD Function 0 Jack sense mode—JS0INT must be polled by software Default JS0MD (JS0 Mode) 1 Interrupt mode—codec will generate an interrupt on JS0 event This bit selects the operation mode for JS1. JS1MD Function 0 Jack sense mode—JS1INT must be polled by software Default JS1MD (JS1 Mode) 1 Interrupt mode—codec will generate an interrupt on JS1 event This bit enables JS0 to control the EQ bypass. When this bit is set to 1, JS0 = 1 will cause the EQ to be bypassed. JS0EQB Function 0 JS0 does not affect EQ Default JS0EQB (JS0 EQ Bypass Enable) 1 JS0 = 1 will cause the EQ to be bypassed This bit enables JS1 to control the EQ bypass. When this bit is set to 1, JS1=1 will cause the EQ to be bypassed. JS1EQB Function 0 JS1 does not affect EQ Default JS1EQB (JS1 EQ Bypass Enable) 1 JS1 = 1 will cause the EQ to be bypassed |
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