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AD1986ABSTZ Datasheet(PDF) 36 Page - Analog Devices |
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AD1986ABSTZ Datasheet(HTML) 36 Page - Analog Devices |
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36 / 56 page  AD1986A Rev. 0 | Page 36 of 56 SPDIF CONTROL (REGISTER 0x3A) Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V-case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in Register 0x2A is 0). This ensures that control and status information start up correctly at the beginning of SPDIF transmission. Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x3A SPDIF Control V VCFG SPSR x L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUDIO PRO 20000x Table 98. Register Function Indicates professional use of the audio stream. PRO State Default 0 Consumer use of channel Default PRO (Professional) 1 Professional use of channel Indicates that the data is PCM or another format (such as AC3). /AUDIO State 0 Data in PCM format Default /AUDIO (Nonaudio) 1 Data in non-PCM format Allows receivers to make copies of the digital data. COPY State 0 Copyright asserted Default COPY (Copyright) 1 Copyright not asserted Disables filter pre-emphasis. PRE State 0 Filter pre-emphasis is 50/15 µsec Default PRE (Pre-emphasis) 1 No pre-emphasis CC [6:0] (Category Code) Programmed according to IEC standards, or as appropriate. L (Generation Level) Programmed according to IEC standards, or as appropriate. Chooses between 48.0 kHz and 44.1 kHz S/PDIF transmitter rate. SPSR Transmit Sample Rate 0 44.1 kHz SPSR (SPDIF Transmit Sample Rate) 1 48.0 kHz Default When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be controlled by the validity bit (D15) in Register 0x3A (SPDIF control register). VCFG V Validity Bit State Reset Default: 0 0 0 Managed by codec error detection logic Default 0 1 Forced high, indicating subframe data is invalid 1 0 Forced low, indicating subframe data is valid VCFG (Validity Force Bit) 1 1 Forced high, indicating subframe data is invalid V (Validity) This bit affects the validity flag, (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. Note that the VCFG bit (0x3A D14) will force the validity flag high (valid) or low (invalid). See the VCFG bit description. V State 0 Each SPDIF subframe (L+R) has Bit 28 set to 1 Default This tags both samples as invalid 1 Each SPDIF subframe (L+R) has Bit 28 set to 0 for valid data and 1 for invalid data (error condition) x Reserved. Default: 0 |
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