HCS12 datasheet(107/126 Pages) NXP

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Device User Guide — 9S12KT256DGV1/D V01.09

107

Freescale Semiconductor

A.7.3 Phase Locked Loop

The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)

is also the system clock source in self clock mode.

A.7.3.1 XFC Component Selection

This section describes the selection of the XFC components to achieve a good filter characteristics.

Figure A-3 Basic PLL functional diagram

The following procedure can be used to calculate the resistance and capacitance values using typical

values for K1, f1 and ich from Table A-20.

The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used

for fOSC = 4MHz and a 25MHz bus clock.

The VCO Gain at the desired VCO frequency is approximated by:

The phase detector relationship is given by:

2. Only valid if

full swing Pierce oscillator/external clock mode is selected

3. fOSC = 4MHz, C = 22pF.

4. Maximum value is for extreme cases using high Q, low frequency crystals

fosc

refdv+1

fref

Phase

Detector

VCO

synr+1

fvco

Loop Divider

KΦ

∆

fcmp

VDDPLL

XFC Pin

1 e

vco

–

()

⋅

-----------------------

⋅

100

–

()

100

–

------------------------

⋅

= -90.48MHz/V

HCS12 Datasheet(PDF) 107 Page - NXP Semiconductors

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