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DP83251 Datasheet(PDF) 28 Page - National Semiconductor (TI) |
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DP83251 Datasheet(HTML) 28 Page - National Semiconductor (TI) |
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28 / 96 page ![]() 50 Registers (Continued) CURRENT TRANSMIT STATE REGISTER (CTSR) (Continued) Bit Symbol Description D3 D4 IC0 IC1 Injection Control k0 1l These bits select one of the 4 injection modes The injection modes overwrite data from the Smoother Repeat Filter Encoder and Transmit Modes IC0 is the only bit of the register that is automatically cleared by the PLAYER device after the One Shot Injection is executed The automatic clear of IC0 during the One Shot mode can be interpreted as an acknowledgment that the One Shot has been completed IC1 IC0 00 No Injection The normal transmission of incoming PHY Request data (ie symbols are not injected) 01 One Shot In one shot mode Injection Symbol Register A (ISRA) and Injection Symbol Register B (ISRB) are injected n symbol pairs after a JK where n is the programmed value of the Injection Count Register (IJCR) If IJCR is set to 0 the JK symbol pair is replaced by ISRA and ISRB Once the One Shot is executed the PLAYER device automatically sets IC0 to 0 thereby returning to normal transmission of data 10 Periodic In Periodic mode Injection Symbol Register A (ISRA) and Injection Symbol Register B (ISRB) are injected every (na1)th symbol pair where n is the programmed value of the Injection Count Register (IJCR) If IJCR is set to 0 all data symbols are replaced with ISRA and ISRB 11 Continuous In Continuous mode all data symbols are replaced with Injection Symbol Register A (ISRA) and Injection Symbol Register B (ISRB) D5 SE SMOOTHER ENABLE 0 Disables the Smoother 1 Enables the Smoother When enabled the Smoother can redistribute Idle symbol pairs which were added or deleted by the local or upstream receivers Note Once the counter has started it will continue to count irrespective of the incoming symbols with the exception of a JK symbol pair This bit should be enabled for interoperable operation D6 PRDPE PHY REQUEST DATA PARITY ENABLE 0 Disables PHY Request Data parity 1 Enables PHY Request Data parity D7 RES RESERVED Reserved for future use Note Users are discouraged from using this bit The reserved bit is set to 1 during the reset process It may be set or cleared without any effects to the functionality of the PLAYER device 28 |
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