DP83251 datasheet(75/96 Pages) NSC

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60 Pin Descriptions (Continued)

MISCELLANEOUS INTERFACE

The Miscellaneous Interface consists of a reset signal user definable sense signals user definable enable signals Cascaded

PLAYER device’s synchronization signals ground signals and power signals

Symbol

Pin No

Description

RST

111

Reset

An active low TTL input signal which clears all registers The signal must be kept

asserted for a minimum of 160 ns

Once the RST signal is asserted the PLAYER device should be allowed 960 ns to reset

internal logic Note that bit zero of the Mode Register will be set to zero (ie Stop Mode)

See Section 42 Stop Mode of Operation for more information

SP0

User Definable Sense Pin 0

A TTL input signal from a user defined source Bit zero

(Sense Bit 0) of the User Definable Register (UDR) will be set to one if the signal is

asserted for a minimum of 160 ns

Once the asserted signal is latched Sense Bit 0 can only be cleared through the Control

Bus Interface even if the signal is deasserted This ensures that the Control Bus

Interface will record the source of events which can cause interrupts

SP1

User Definable Sense Pin 1

A TTL input signal from a user defined source Bit one

(Sense Bit 1) of the User Definable Register (UDR) will be set to one if the signal is

asserted for a minimum of 160 ns

Once the asserted signal is latched Sense Bit 0 can only be cleared through the Control

Bus Interface even if the signal is deasserted This ensures that the Control Bus

Interface will record the source of events which can cause interrupts

EP0

User Definable Enable Pin 0

A TTL output signal allowing control of external logic

through the Control Bus Interface EP0 is asserteddeasserted through bit two (Enable

Bit 0) of the User Definable Register (UDR) When Enable Bit 0 is set to zero EP0 is

deasserted When Enable Bit 0 is set to one EP0 is asserted

EP1

User Definable Enable Pin 1

A TTL output signal allowing control of external logic

through the Control Bus Interface EP1 is asserteddeasserted through bit two (Enable

Bit 1) of the User Definable Register (UDR) When Enable Bit 1 is set to zero EP1 is

deasserted When Enable Bit 1 is set to one EP1 is asserted

Cascade Start

A TTL input signal used to synchronize cascaded PLAYER devices in

point-to-point applications

The signal is asserted when all of the cascaded PLAYER devices have the Cascade

Mode (CM) bit of the Mode Register (MR) set to one and all of the Cascade Ready (CR)

pins of the cascaded PLAYER devices have been released

For further information refer to Section 44 Cascade Mode of Operation

Cascade Ready

An Open Drain output signal used to synchronize cascaded PLAYER

devices in point-to-point applications

The signal is released when all the cascaded PLAYER devices have the Cascade Mode

(CM) bit of the Mode Register (MR) set to one and a JK symbol pair has been received

For further information refer to section 44 Cascade Mode of Operation

DP83251 Datasheet(PDF) 75 Page - National Semiconductor (TI)

DP83251 Datasheet(HTML) 75 Page - National Semiconductor (TI)

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