ADP3191 datasheet(14/28 Pages) AD

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ADP3191

Rev. 0 | Page 14 of 28

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 10.1-compliant

CPU application are as follows:

•

Input voltage (VIN) = 12 V

•

VID setting voltage (VVID) = 1.300 V

•

Duty cycle (D) = 0.108

•

Nominal output voltage at no load (VONL) = 1.281 V

•

Nominal output voltage at 101 A load (VOFL) = 1.180 V

•

Static output voltage drop based on a 1.0 mΩ load line (RO)

from no load to full load (VD) = VONL − VOFL =

1.281 V − 1.180 V = 101 mV

•

Maximum output current (IO) = 119 A

•

Maximum output current step (ΔIO) = 95 A

•

Number of phases (n) = 4

•

Switching frequency per phase (fSW) = 330 kHz

SETTING THE CLOCK FREQUENCY

The ADP3191/ADP3191A use a fixed-frequency control

architecture. The frequency is set by an external timing resistor

(RT). The clock frequency and the number of phases determine

the switching frequency per phase, which relates directly to

switching losses and the sizes of the inductors and/or the input

and output capacitors. With n = 4 for four phases, a clock

frequency of 1.32 MHz sets the switching frequency (fSW) of

each phase to 330 kHz, which represents a practical trade-off

between the switching losses and the sizes of the output filter

components. Figure 3 shows that to achieve 1.32 MHz oscillator

frequency, the correct value for RT is 130 kΩ. Alternatively, the

value for RT can be calculated using

−

(1)

where 4.7 pF and 31 kΩ are internal IC component values. For

good initial accuracy and frequency stability, a 1% resistor is

recommended.

SOFT START AND CURRENT-LIMIT LATCH-OFF

DELAY TIMES

Because the soft start and current-limit latch-off delay functions

share the DELAY pin, these two parameters must be considered

together. The first step is to set CDLY for the soft start ramp. This

ramp is generated with a 20 μA internal current source. The

value of RDLY has a second-order impact on the soft start time

because it sinks part of the current source to ground.

However, as long as RDLY is kept greater than 200 kΩ, this effect

is minor. The value for CDLY can be approximated using

VID

DLY

VID

DLY

⎟

⎠

⎞

⎜

⎝

⎛

−

(2)

where tSS is the desired soft start time. Assuming an RDLY of

390 kΩ and a desired soft start time of 3 ms, CDLY is 36 nF.

The closest standard value for CDLY is 39 nF. Once CDLY is

chosen, RDLY can be calculated for the current-limit latch-off

time using

DLY

DELAY

DLY

(3)

If the result for RDLY is less than 200 kΩ, a smaller soft start time

should be considered by recalculating the equation for CDLY, or

a longer latch-off time should be used. RDLY should never be less

than 200 kΩ. In this example, a delay time of 9 ms results in

RDLY = 452 kΩ. The closest standard 5% value is 470 kΩ.

INDUCTOR SELECTION

The choice of inductance for the inductor determines the ripple

current in the inductor. Less inductance leads to more ripple

current, which increases the output ripple voltage and conduction

losses in the MOSFETs. But it also allows using smaller inductors

and, for a specified peak-to-peak transient deviation, less total

output capacitance.

Conversely, a higher inductance means lower ripple current and

reduced conduction losses but requires larger inductors and

more output capacitance for the same peak-to-peak transient

deviation. In any multiphase converter, a practical value for the

peak-to-peak inductor ripple current is less than 50% of the

maximum dc current in the same inductor. Equation 4 shows the

relationship between the inductance, oscillator frequency, and

peak-to-peak ripple current in the inductor.

(

)

VID

−

(4)

Equation 5 can be used to determine the minimum inductance

based on a given output ripple voltage.

(

)

(

)

RIPPLE

VID

−

≥

(5)

Solving Equation 5 for a 10 mV p-p output ripple voltage yields

(

)

224

kHz

330

0.432

mΩ

1.0

1.3

−

≥

If the resulting ripple voltage is less than it was designed for,

make the inductor smaller until the ripple value is met.

This allows optimal transient response and minimum output

decoupling.

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