ADP3191 datasheet(26/28 Pages) AD

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ADP3191

Rev. 0 | Page 26 of 28

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal per-

formance of a switching regulator in a PC system.

GENERAL RECOMMENDATIONS

•

For good results, a PCB with at least four layers is

recommended. This allows the needed versatility for

control circuitry interconnections with optimal placement;

power planes for ground, input, and output power; and

wide interconnection traces in the remainder of the power

delivery current paths.

Note: Each square unit of 1 ounce copper trace has a

resistance of ~0.53 mΩ at room temperature.

•

Whenever high currents must be routed between PCB

layers, vias should be used liberally to create several

parallel current paths. Then, the resistance and inductance

introduced by these current paths is minimized, and the

via current rating is not exceeded.

•

If critical signal lines, including the output voltage sense

lines of the ADP3191/ADP3191A, must cross through

power circuitry, it is best if a signal ground plane can be

interposed between those signal lines and the traces of the

power circuitry. This serves as a shield to minimize noise

injection into the signals at the expense of making signal

ground noisier.

•

Use an analog ground plane around and under the

ADP3191/ADP3191A as a reference for the components

associated with the controller. This plane should be tied to

the nearest output decoupling capacitor ground and not tied

to any other power circuitry. This prevents power currents

from flowing in the ground plane.

•

Locate the components around the ADP3191/ADP3191A

close to the controller with short traces. The most

important traces to keep short, and away from other traces,

are the FB pin and the CSSUM pin. Connect the output

capacitors as close as possible to the load (or connector),

for example, a microprocessor core that receives the power.

If the load is distributed, the capacitors should also be

distributed and generally be in proportion to where the

load tends to be more dynamic.

•

Avoid crossing any signal lines over the switching power

path loop, as described in the Power Circuitry

Recommendations section.

POWER CIRCUITRY RECOMMENDATIONS

•

The switching power path should be routed on the PCB

to encompass the shortest possible length to minimize

radiated switching noise energy (that is, EMI) and

conduction losses in the board. Failure to take proper

precautions often results in EMI problems for the entire

PC system as well as noise-related operational problems in

the power converter control circuitry. The switching power

path is the loop formed by the current path through the

input capacitors and the power MOSFETs, including all

interconnecting PCB traces and planes. Using short and

wide interconnection traces is especially critical in this path

for two reasons: it minimizes the inductance in the switching

loop, which can cause high energy ringing; and it accom-

modates the high current demand with minimal voltage loss.

•

Whenever a power dissipating component, (for example,

a power MOSFET), is soldered to a PCB, the liberal use of

vias, both directly on the mounting pad and immediately

surrounding it, is recommended. This improves current

rating through the vias and also improves thermal

performance from vias extended to the opposite side of the

PCB, where a plane can more readily transfer the heat to the

air. Make a mirror image of any pad being used to heat-

sink the MOSFETs on the opposite side of the PCB to

achieve the best thermal dissipation to the air around the

board. To further improve thermal performance, use the

largest possible pad area.

•

The output power path should also be routed to encompass

a short distance. The output power path is formed by the

current path through the inductor, the output capacitors,

and the load.

•

For best EMI containment, a solid power ground plane

should be used as one of the inner layers extending fully

under all the power components.

SIGNAL CIRCUITRY RECOMMENDATIONS

•

The output voltage is sensed and regulated between the

FB pin and the FBRTN pin, which connect to the signal

ground at the load. To avoid differential-mode noise pickup in

the sensed signal, the loop area should be small. Thus, the

FB and FBRTN traces should be routed adjacent to each

other on top of the power ground plane back to the controller.

•

The feedback traces from the switch nodes should be

connected as close as possible to the inductor. The CSREF

signal should be connected to the output voltage at the

nearest inductor to the controller.

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