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ADP3191

Rev. 0 | Page 17 of 28

COUT SELECTION

The required output decoupling for the regulator is typically

recommended by Intel for various processors and platforms.

Also, to determine what is required, use some simple design

guidelines that are based on having both bulk and ceramic

capacitors in the system.

The first step is to select the total amount of ceramic capaci-

tance. This is based on the number and type of capacitor to be

used. The best location for ceramic capacitors is inside the

socket, with 12 to 18 of Size 1206 being the physical limit.

Additional ceramic capacitors can be placed along the outer

edge of the socket as well.

Combined ceramic values of 200 μF to 300 μF are recommended,

usually made up of multiple 10 μF or 22 μF capacitors. Select

the number of ceramic capacitors, and find the total ceramic

capacitance (CZ).

Next, there is an upper limit imposed on the total amount of

bulk capacitance (CX) when considering the VID on-the-fly

voltage stepping of the output (Voltage Step VV in Time tV with

error of VERR). A lower limit is based on meeting the capaci-

tance for load release for a given maximum load step, ∆IO, and

a maximum allowable overshoot. The total amount of load

release voltage is given as ΔVO = ΔIO × RO + ΔVrl, where ΔVrl

is the maximum allowable overshoot voltage.

()

⎟

⎠

⎞

⎜

⎝

⎛

−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

≥

VID

MIN

(12)

() ≤

MAX

VID

nKR

−

⎟

⎠

⎞

⎜

⎝

⎛

−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

(13)

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

ERR

where

To meet the conditions of these expressions and transient

response, the ESR of the bulk capacitor bank (RX) should be less

than two times the droop resistance (RO). If the CX(MIN) is larger

than CX(MAX), the system cannot meet the VID on-the-fly speci-

fication and may require the use of a smaller inductor or more

phases (and may need the switching frequency to increase to

keep the output ripple the same).

This example uses 18, 10 μF 1206 MLC capacitors (CZ = 180 μF).

The VID on-the-fly step change is 450 mV in 230 μs with a

settling error of 2.5 mV. The maximum allowable load release

overshoot for this example is 50 mV, so solving for the bulk

capacitance yields

()

μF

180

mΩ

320

⎟

⎠

⎞

⎜

⎝

⎛

−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

≤

MIN

()

≤

Ω

450

320

MAX

180

320

450

1.0

4.6

1.3

μs

230

−

⎟

⎠

⎞

⎜

⎝

⎛

−

⎟

⎠

⎞

⎜

⎝

⎛

48.5 mF

where K = 4.6.

Using eight 560 μF Al-Poly capacitors with a typical ESR

of 5 mΩ each yields CX = 4.48 mF with an RX = 0.63 mΩ.

One last check should be made to ensure that the ESL of the

bulk capacitors (LX) is low enough to limit the high frequency

ringing during a load change. This is tested using

()

360

mΩ

μF

180

≤

(14)

where Q is limited to the square root of 2 to ensure a critically

damped system. In this example, LX is approximately 350 pH

for the eight A1-Polys capacitors, which satisfies this limitation.

If the LX of the chosen bulk capacitor bank is too large, the

number of ceramic capacitors may need to be increased if

there is excessive ringing.

For this multimode control technique, all ceramic designs can

be used as long as the conditions of Equation 11, Equation 12,

and Equation 13 are satisfied.

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