ADP3191 datasheet(18/28 Pages) AD

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ADP3191

Rev. 0 | Page 18 of 28

POWER MOSFETS

For this example, the N-channel power MOSFETs have been

selected for one high-side switch and two low-side switches per

phase. The main selection parameters for the power MOSFETs

are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive

voltage (the supply voltage to the ADP3110A) dictates whether

standard threshold or logic-level threshold MOSFETs must be

used. With VGATE ~10 V, logic-level threshold MOSFETs

(VGS(TH)° < 2.5 V) are recommended.

The maximum output current (IO) determines the RDS(ON)

requirement for the low-side (synchronous) MOSFETs. With

the ADP3191/ADP3191A, currents are balanced between

phases; thus, the current in each low-side MOSFET is the

output current divided by the total number of MOSFETs (nSF).

With conduction losses being dominant, the following

expression shows the total power being dissipated in each

synchronous MOSFET in terms of the ripple current per phase

(IR) and average total output current (IO):

()

⎥

⎦

⎤

⎢

⎣

⎡

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

−

(15)

Knowing the maximum output current being designed for and

the maximum allowed power dissipation, it is possible to find

the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up

to an ambient temperature of 50°C, a safe limit for PSF is 1 W to

1.5 W at 120°C junction temperature. Thus, for this example

(119 A maximum), RDS(SF) (per MOSFET) < 7.5 mΩ. This RDS(SF)

is also at a junction temperature of about 120°C, so be certain to

account for this temperature when making this selection. This

example uses two lower-side MOSFETs at 4.8 mΩ each at 120°C.

Another important factor for the synchronous MOSFET is the

input capacitance and feedback capacitance. The ratio of the

feedback to input needs to be small (less than 10% is recom-

mended) to prevent accidental turn-on of the synchronous

MOSFETs when the switch node goes high.

Also, the time to switch the synchronous MOSFETs off should

not exceed the nonoverlap dead time of the MOSFET driver

(40 ns typical for the ADP3110A). The output impedance of the

driver is approximately 2 Ω, and the typical MOSFET input gate

resistances are about 1 Ω to 2 Ω, so a total gate capacitance of

less than 6000 pF should be adhered to. Because there are two

MOSFETs in parallel, the input capacitance for each synchronous

MOSFET should be limited to 3000 pF.

The high-side (main) MOSFET has to be able to handle two

main power dissipation components: conduction and switching

losses. The switching loss is related to the amount of time it

takes for the main MOSFET to turn on and off and to the

current and voltage that are being switched.

Basing the switching speed on the rise and fall time of the gate

driver impedance and MOSFET input capacitance, the follow-

ing expression provides an approximate value for the switching

loss per main MOSFET, where nMF is the total number of main

MOSFETs:

()

ISS

= 2

(16)

where RG is the total gate resistance (2 Ω for the ADP3110A and

about 1 Ω for typical high speed switching MOSFETs, making

RG = 3 Ω), and CISS is the input capacitance of the main MOSFET.

Adding more main MOSFETs (nMF) does not really help the

switching loss per MOSFET because the additional gate

capacitance slows switching. The best way to reduce switching

loss is to use lower gate capacitance devices.

The conduction loss of the main MOSFET is given by the

following, where RDS(MF) is the on resistance of the MOSFET:

()

⎥

⎦

⎤

⎢

⎣

⎡

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛ ×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

(17)

Typically, for main MOSFETs, the highest speed (low CISS)

device is preferred, but these usually have higher on resistance.

Select a device that meets the total power dissipation (about

1.5 W for a single D-PAK) when combining the switching and

conduction losses.

For this example, an NTD40N03L was selected as the main

MOSFET (eight total; nMF = 8), with a CISS = 584 pF (maximum)

and RDS(MF) = 19 mΩ (maximum at TJ = 120°C). An NTD110N02L

was selected as the synchronous MOSFET (eight total; nSF = 8),

with CISS = 2710 pF (maximum) and RDS(SF) = 4.8 mΩ (maximum

at TJ = 120°C). The synchronous MOSFET CISS is less than 3000 pF,

satisfying that requirement. Solving for the power dissipation per

MOSFET at IO = 119 A and IR = 11 A yields 958 mW for each

synchronous MOSFET and 872 mW for each main MOSFET.

These numbers comply with the guideline to limit the power

dissipation to 1 W per MOSFET.

One last thing to consider is the power dissipation in the driver

for each phase. This is best described in terms of the QG for the

MOSFETs and is given by the following equation, where QGMF is

the total gate charge for each main MOSFET, and QGSF is the

total gate charge for each synchronous MOSFET:

()

GSF

GMF

DRV

⎥

⎦

⎤

⎢

⎣

⎡

(18)

Also shown is the standby dissipation factor (ICC × VCC) for the

driver. For the ADP3110A, the maximum dissipation should be

less than 400 mW. In this example, with ICC = 7 mA, QGMF =

5.8 nC, and QGSF = 48 nC, 297 mW is found in each driver,

which is below the 400 mW dissipation limit. See the

ADP3110A data sheet for more details.

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