ADP3191 datasheet(19/28 Pages) AD

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ADP3191

Rev. 0 | Page 19 of 28

RAMP RESISTOR SELECTION

The ramp resistor (RR) is used for setting the size of the internal

PWM ramp. The value of this resistor is chosen to provide the

best combination of thermal balance, stability, and transient

response. The following expression is used for determining the

optimum value:

kΩ

356

Ω

2.4

320

0.2

(19)

where AR is the internal ramp amplifier gain, AD is the current

balancing amplifier gain, RDS is the total low-side MOSFET on

resistance, and CR is the internal ramp capacitor value. The

closest standard 1% resistor value is 357 kΩ.

The internal ramp voltage magnitude can be calculated by using

()

390

kHz

330

Ω

357

1.3

0.108

0.2

−

VID

(20)

The size of the internal ramp can be made larger or smaller. If it

is made larger, stability and transient response improve, but

thermal balance degrades. Likewise, if the ramp is made

smaller, thermal balance improves at the sacrifice of transient

response and stability. The factor of 3 in the denominator of

Equation 19 sets a ramp size that gives an optimal balance for

good stability, transient response, and thermal balance.

COMP PIN RAMP

A ramp signal on the COMP pin is due to the droop voltage and

output voltage ramps. This ramp amplitude adds to the internal

ramp to produce the following overall ramp signal at the PWM

input:

()

⎟

⎠

⎞

⎜

⎝

⎛

−

(21)

In this example, the overall ramp signal is 0.49 V.

CURRENT-LIMIT SETPOINT

To select the current-limit setpoint, first find the resistor value

for RLIM. The current-limit threshold for the ADP3191/ADP3191A

is set with a 3 V source (VLIM) across RLIM with a gain of

10.4 mV/μA (ALIM). RLIM can be found using

LIM

(22)

For values of RLIM greater than 500 kΩ, the current limit can be

lower than expected, so some adjustment of RLIM may be needed.

Here, ILIM is the average current limit for the output of the supply.

In this example, choosing a peak current limit of 200 A for ILIM

results in RLIM = 156 kΩ, for which 150 kΩ is chosen as the

nearest 1% value.

The limit of the per-phase current limit described earlier is

determined by

()

MAX

BIAS

MAX

COMP

PHLIM

−

≅

(23)

For the ADP3191/ADP3191A, the maximum COMP voltage

(VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V,

and the current-balancing amplifier gain (AD) is 5. Using VR of

0.49 V and RDS(MAX) of 3 mΩ (low-side on resistance at 150°C),

calculate a per-phase peak current limit of 100 A. Although this

number may seem high, this current level can be reached only

with an absolute short at the output, and the current-limit latch-

off function shuts down the regulator before overheating can

occur.

This limit can be adjusted by changing the ramp voltage (VR),

but make sure not to set the per-phase limit lower than the

average per-phase current (ILIM/n).

The per-phase initial duty cycle limit is determined by

()

BIAS

MAX

COMP

MAX

−

(24)

In this example, the maximum duty cycle is 0.46.

FEEDBACK LOOP COMPENSATION DESIGN

Optimized compensation of the ADP3191/ADP3191A allows

the best possible response of the regulator’s output to a load

change. The basis for determining the optimum compensation

is to make the regulator and output decoupling appear as an

output impedance that is entirely resistive over the widest

possible frequency range, including dc, and equal to the droop

resistance (RO).

With the resistive output impedance, the output voltage droops

in proportion to the load current at any load current slew rate.

This ensures optimal positioning and allows minimization of

the output decoupling.

With the multimode feedback structure of the ADP3191/

ADP3191A, the feedback compensation must be set to make

the converter’s output impedance, working in parallel with the

output decoupling, meet this goal. Several poles and zeros

created by the output inductor and decoupling capacitors

(output filter) need to be compensated for.

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