TMPR4925 datasheet(391/590 Pages) TOSHIBA

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Chapter 12 Timer/Counter

12-3

12.3 Detailed Explanation

12.3.1

Overview

The TX4925 has an on-chip 3-channel 32-bit timer/counter. Each channel supports the following

modes.

(1) Interval Timer Mode (Timer 0, 1, 2)

This mode periodically generates interrupts.

(2) Pulse Generator Mode (Timer 0, 1)

This is the pulse signal output mode.

(3) Watchdog Timer Mode (Timer 2)

This mode is used to monitor system abnormalities.

12.3.2

Counter Clock

The clock used for counting can be set to a frequency that is 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, or

1/256 of the internal clock (IMBUSCLK) frequency, or can be selected from nine counter input signal

(TCLK) types. Divide Register n (TMCCDRn) and the Counter Clock Select bit (TMTCRn.CCS) are

used to select the counter clock. In this situation, IMBUSCLK is the internal clock signal which is the

G-Bus clock divided by 2. See “Chapter 6 Clocks” for more information.

The counter input signal (TCLK) is used by three channels. Using TCLK makes it possible to count

external events. The External Clock Edge bit (TMTCRn.ECES) can be used to select the clock

rising/falling count.

Set the TCLK clock frequency to 45% or less of IMBUSCLK (TCLK = 18 MHz or less when

IMBUSCLK = 40 MHz). The following table shows example count times when using 40 MHz

IMBUSCLK.

Table 12.3.1 Divide Value and Count (IMBUSCLK = 40 MHz)

Divide

Rate

TMCCDRn.

CCD

Counter Clock

Frequency (Hz)

Resolution (ns)

Max. Set Time

(sec.)

TMCPRAn Value

for 1 sec.

128

256

000

001

010

011

100

101

110

111

20.0 M

10.0 M

5.0 M

2.5 M

1.25 M

625.0 K

312.5 K

156.25 K

50.00

100.00

200.00

400.00

800.00

1600.00

3200.00

6400.00

214.75

429.50

858.99

1717.99

3435.97

6871.95

13743.90

27487.79

20000000

10000000

5000000

2500000

1250000

625000

312500

156250

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