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TMPR4925 Datasheet(PDF) 242 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 242 Page - Toshiba Semiconductor |
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242 / 590 page  Chapter 9 SDRAM Controller 9-14 Bits Mnemonic Field Name Description 3:1 CS Column Size Column Size (Initial value: {0,(ADDR[11,12] & (ADDR[8:6]==000))}/000, R/W) Specifies the column size. If ADDR[8:6] are 000 during the boot sequence to select SyncFlash as the boot memory, the value of ADDR[11,12] during the boot sequence are set in CS[1:0]. CS[2] is zero. 000: 256 words (8 bits) 001: 512 words (9 bits) 010: 1024 words (10 bits) 011: 2048 words (11 bits) 100: 4096 words (12 bits) 101 – 111: Reserved 0 MW Memory Width Memory Width (Initial value: (ADDR[13] & (ADDR[8:6]==000))/0, R/W) Specifies the bus width. If ADDR[8:6] are 000 during the boot sequence to select SyncFlash as the boot memory, the value of ADDR[13] during the boot sequence is set in this bit. 0: 32 bits 1: 16 bits Figure 9.4.1 SDRAM Channel Control Register (2/2) |
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