TMPR4925 datasheet(306/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-44

10.4.18 P2G Configuration Register (P2GCFG)

0xD090

Reserved

: Type

: Initial value

321

Reserved

FTRD

FTA TOBFR TIBFR

R/W

R/W : Type

: Initial value

Bits

Mnemonic

Field Name

Description

31:5



Reserved



Reserved

Don’t write one in this bit (Initial value: 0, R/W).

FTRD

Force Target

Retry/Disconnect

Force Target Retry/Disconnect (Initial value: 0, R/W)

The PCI Controller executes Retry Termination on a PCI Read access transaction if

this bit is set to “1”. This is a diagnostic function.

FTA

Force Target

Abort

Force Target Abort (Initial value: 0, R/W)

The PCI Controller executes a Target Abort on a PCI Read access transaction if this

bit is set to “1”. This is a diagnostic function.

TOBFR

Target read FIFO

Reset

Target read FIFO Reset (Initial value: 0, R/W)

The PCI Controller flushes the CORE internal Target Out-Bound FIFO when “1” is

written to this bit. This bit always reads out “0” when it is read. This is a diagnostic

function.

TIBFR

Target write FIFO

Reset

Target write FIFO Reset (Initial value: 0, R/W)

The PCI Controller flushes the CORE internal Target In-Bound FIFO when “1” is

written to this bit. This bit always read out “0” when it is read. This is a diagnostic

function.

Figure 10.4.18 P2G Configuration Register

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