THS7313 datasheet(35/48 Pages) TI

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Channel Register Bit Descriptions

EXAMPLE – WRITING TO THE THS7313

THS7313

SLOS483 – NOVEMBER 2005

Each bit of the sub-address (channel selection) control register as described above allows the user to individually

control the functionality of the THS7313. The benefit of this process allows the user to control the functionality of

each channel independent of the other channels. The bit description is decoded in Table 3.

Table 3. THS7313 Channel Register Bit Decoder Table

BIT

FUNCTION

BIT

RESULT

VALUE(S)

(MSB)

STC Low Pass Filter Selection

0 0

500-kHz Filter – Useful for poor video sync signals

7, 6

0 1

2.5-MHz Filter – Useful for reasonable sync signals

1 0

5-MHz Filter – Useful for good sync signals

1 1

5-MHz Filter – Useful for good sync signals

Input MUX Selection

Input A Select

Input B Select

4 , 3

Reserved

X X

Do Not Care

2, 1, 0

Input Bias Mode Selection and

0 0 0

Disable Channel – Conserves Power

(LSB)

Disable Control

0 0 1

Channel On – Mute Function – No Output

0 1 0

Channel On – DC Bias Select

0 1 1

Channel On – DC Bias + 135 mV Offset Select

1 0 0

Channel On – AC Bias Select

1 0 1

Channel On – Sync Tip Clamp with Low Bias

1 1 0

Channel On – Sync Tip Clamp with Mid Bias

1 1 1

Channel On – Sync Tip Clamp with High Bias

Bits 7 (MSB) and 6 – Controls the AC-Sync Tip Clamp Low Pass Filter function. If AC-STC mode is not used,

this function is ignored.

Bit 5 – Controls the input MUX of the THS7313.

Bits 4 and 3 – Reserved for future functionality. The values of these bits do not affect the THS7313.

Bits 2, 1, and 0 (LSB) – Selects the input biasing of the THS7313 and the power-savings function. When

Sync-Tip Clamp is selected, the DC input sink bias current is also selectable.

The proper way to write to the THS7313 is illustrated as follows:

An I2C master initiates a write operation to the THS7313 by generating a start condition (S) followed by the

THS7313 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After

receiving an acknowledge from the THS7313, the master presents the subaddress (channel) it wants to write

consisting of one byte of data, MSB first. The THS7313 acknowledges the byte after completion of the

transfer. Finally the master presents the data it wants to write to the register (channel) and the THS7313

acknowledges the byte. The I2C master then terminates the write operation by generating a stop condition

(P). Note that the THS7313 does not support multi-byte transfers. To write to all three channels – or registers

– this procedure must be repeated for each register one series at a time (i.e., repeat steps 1 through 8 for

each channel).

Step 1

I2C Start (Master)

Step 2

I2C General Address (Master)

Where each X Logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND.

Step 3

I2C Acknowledge (Slave)

THS7313 Datasheet(PDF) 35 Page - Texas Instruments

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