THS7313 datasheet(19/48 Pages) TI

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GND

CH.2 IN B

CH.3 IN B

I 2C-A0

SDA

VS+ 11

SCL

CH. 3 SAG

I 2C-A1

CH.1 IN B

CH.2 IN A

CH.3 IN A

CH.1 IN A

CH.3 OUT

CH. 2 SAG

CH.2 OUT

CH. 1 SAG

CH.1 OUT

DAC /

Encoder

(THS8200)

3.3 V

CVBS

Y’

C’

75 W

0.1 F

0.01 F

100 F

0.1 F

CVBS

Out

470 F

0.1 F

(See Note A)

+Vs

I C

Controller

SDTV

CVBS

S-Video Y’

S-Video C’

480i

576i

G’B’R’

AC STC

AC Bias

DC + 135 mV

External

Input

CVBS

S-Video C’

S-Video Y’

75 W

C’

Out

Y’

Out

S-Video

INPUT MODES OF OPERATION – DC

THS7313

SLOS483 – NOVEMBER 2005

APPLICATION INFORMATION (continued)

Due to the high frequency content of the video signal, it is recommended, but not required, to add a 0.01-

µF capacitor

in parallel with these large capacitors.

Figure 47. Typical SDTV CVBS/Y'/C' Inputs From DC-Coupled Encoder/DAC and

AC-Coupled External Inputs With AC-Coupled Line Driving

The inputs to the THS7313 allows for both ac coupled and dc coupled inputs. Many DAC’s or video encoders

can be dc connected to the THS7313. But, one of the drawbacks to dc coupling is when 0 V is applied to the

input of the THS7313. Although the input of the THS7313 allows for a 0-V input signal, the output swing of the

THS7313 cannot yield a 0-V signal. This applies to any traditional single-supply amplifier due to the limitations of

the output transistors. Both CMOS and bipolar transistors cannot go to 0 V while sinking a significant amount of

current. This trait of a transistor is also the same reason why the highest output voltage is always less than the

power supply voltage when sourcing a significant amount of current.

The internal gain is fixed at 6 dB (2 V/V) regardless of the configuration of the THS7313, and dictates what the

allowable linear input voltage range is without clipping concerns. For example, if the power supply is set to 3 V,

the maximum output is about 2.9 V. Thus, to avoid clipping, the allowable input is 2.9 V / 2 = 1.45 V. This is true

for up to the maximum recommended 5-V power supply that allows about a 4.9 V / 2 = 2.45 V input range while

avoiding clipping on the output.

The input impedance of the THS7313 in this mode of operation is >1 M

Ω. This is due to the input buffer being

configured as a unity gain amplifier as shown in Figure 48.

THS7313 Datasheet(PDF) 19 Page - Texas Instruments

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