THS7313 datasheet(32/48 Pages) TI

Part #	THS7313

Description	3-Channel Low Power SDTV Video Amplifier with I2C Control, 6-dB Gain, SAG Correction, 2:1 Input MUX, and Selectable Input Bias Modes

PDF	48 Pages

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Manufacturer	TI [Texas Instruments]

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SCL

SDA

Data Line

Stable;

Data Valid

Change of Data Allowed

Start

Condition

Clock Pulse for

Acknowledgement

Acknowledge

Not Acknowledge

Data Output

by Receiver

Data Output

by Transmitter

SCL From

Master

SCL

SDA

MSB

Slave Address

Data

Stop

Acknowledge

THS7313

SLOS483 – NOVEMBER 2005

APPLICATION INFORMATION (continued)

Figure 59. I2C Bit Transfer

Figure 60. I2C Acknowledge

Figure 61. I2C Address and Data Cycles

During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so

that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the

receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting

device after the last byte is transferred. An example of a write cycle can be found in Figure 62 and Figure 63.

Note that the THS7313 does not allow multiple write transfers to occur. See example section – Writing to the

THS7313 for more information.

During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its

address. Following this initial acknowledge by the slave, the master device becomes a receiver and

THS7313 Datasheet(PDF) 32 Page - Texas Instruments