IMX7DCEC datasheet(15/161 Pages) NXP

15 / 161 page

Modules list

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

uSDHC1

uSDHC2

uSDHC3

SD/MMC and SDXC

Enhanced Multi-Media

Card / Secure Digital Host

Controller

Connectivity

peripherals

i.MX 7Dual SoC characteristics:

All the MMC/SD/SDIO controller IPs are based on the

uSDHC IP. They are designed to be:

• Fully compatible with MMC command/response sets

and Physical Layer as defined in the Multimedia

Card System Specification,

v5.0/v4.4/v4.41/v4.4/v4.3/v4.2.

• Fully compatible with SD command/response sets

and Physical Layer as defined in the SD Memory

Card Specifications v 3.0 including high-capacity

SDXC cards up to 2 TB.

• Fully compatible with SDIO command/response sets

and interrupt/Read-Wait mode as defined in the

SDIO Card Specification, Part E1, v. 3.0

All the ports support:

• 1-bit or 4-bit transfer mode specifications for SD and

SDIO cards up to UHS-I SDR104 mode (104 MB/s

max)

• 1-bit, 4-bit, or 8-bit transfer mode specifications for

MMC cards up to 200 MHz in both SDR and DDR

modes, including HS200 and HS400.

However, the SoC level integration and I/O muxing logic

restrict the functionality to the following:

• uSDHC1 and uSDHC2 are primarily intended to

serve as external slots or interfaces to on-board

SDIO devices. These ports are equipped with “Card

detection” and “Write Protection” pads and do not

support hardware reset.

• uSDHC3 is primarily intended to serve interfaces to

embedded MMC memory or interfaces to on-board

SDIO devices. These ports do not have “Card

detection” and “Write Protection” pads and do

support hardware reset.

• All ports can work with 1.8 V and 3.3 V cards. There

are two completely independent I/O power domains

for uSDHC1 and uSDHC2 in 4-bit configuration (SD

interface). uSDHC3 is placed in his own independent

power domain.

USBOTG2

2x USB 2.0 High Speed

OTG and HSIC USB

Connectivity

peripherals

USBOTG2 contains:

• Two high-speed OTG modules with integrated HS

USB PHYs

• One high-speed Host module connected to HSIC

USB port.

Table 2. i.MX 7Dual modules list(continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

IMX7DCEC Datasheet(PDF) 15 Page - NXP Semiconductors

IMX7DCEC Datasheet(HTML) 15 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL