IMX7DCEC datasheet(80/161 Pages) NXP

80 / 161 page

Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

Figure 43. Toggle mode data read timing

Table 58. Toggle mode timing parameters1

Parameter

Symbol

Timing

T = GPMI Clock Cycle

Unit

Min.

Max.

NF1 NAND_CLE setup time

tCLS

(AS + DS)  T - 0.12 [see note2s,3]

NF2 NAND_CLE hold time

tCLH

DH  T - 0.72 [see note2]

NF3 NAND_CE0_B setup time

tCS

(AS + DS)  T - 0.58 [see notes,2]

NF4 NAND_CE0_B hold time

tCH

DH  T - 1 [see note2]

NF5 NAND_WE_B pulse width

tWP

DS  T [see note2]

NF6 NAND_ALE setup time

tALS

(AS + DS)  T - 0.49 [see notes,2]

NF7 NAND_ALE hold time

tALH

DH  T - 0.42 [see note2]

NF8 Command/address NAND_DATAxx setup time

tCAS

DS  T - 0.26 [see note2]

NF9 Command/address NAND_DATAxx hold time

tCAH

DH  T - 1.37 [see note2]

NF18 NAND_CEx_B access time

tCE

CE_DELAY  T [see notes4,2]

—

NF22 clock period

tCK

—

NF23 preamble delay

tPRE

PRE_DELAY  T [see notes5,2]

—

NF24 postamble delay

tPOST

POST_DELAY  T +0.43 [see

note2]

—

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