IMX7DCEC datasheet(58/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

Figure 14 to Figure 17 provide few examples of basic EIM accesses to external memory devices with the

timing parameters mentioned previously for specific control parameters settings.

Figure 14. Synchronous memory read access, WSC=1

1 t is the maximum EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency depends on the fixed/non-fixed

latency configuration, whereas the maximum allowed EIM_BCLK frequency is:

—Fixed latency for both read and write is 132 MHz.

—Variable latency for read only is 132 MHz.

—Variable latency for write only is 52 MHz.

In variable latency configuration for write, if BCD = 0 & WBCDD = 1 or BCD = 1, axi_clk must be 104 MHz. Write BCD = 1 and

104 MHz axi_clk, will result in a EIM_BCLK of 52 MHz. When the clock branch to EIM is decreased to 104 MHz, other buses

are impacted which are clocked from this source. See the CCM chapter of the i.MX 7Dual Application Processor Reference

Manual (IMX7DRM) for a detailed clock tree description.

2 EIM_BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is

defined as 50% as signal value.

3 For signal measurements, “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.

Last Valid Address

Address v1

D(v1)

EIM_BCLK

EIM_ADDRxx

EIM_DATAxx

EIM_WE_B

EIM_LBA_B

EIM_OE_B

EIM_EBx_B

EIM_CSx_B

WE4

WE5

WE6

WE7

WE10

WE11

WE13

WE12

WE14

WE15

WE18

WE19

IMX7DCEC Datasheet(PDF) 58 Page - NXP Semiconductors