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IMX7DCEC Datasheet(PDF) 57 Page - NXP Semiconductors |
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IMX7DCEC Datasheet(HTML) 57 Page - NXP Semiconductors |
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57 / 161 page  Electrical characteristics i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023 NXP Semiconductors 57 4.8.3.3 Examples of EIM synchronous accesses Table 45. EIM bus timing parameters 1 ID Parameter BCD = 0 BCD = 1 BCD = 2 BCD = 3 Min Max Min Max Min Max Min Max WE1 EIM_BCLK Cycle time2 t — 2 x t — 3 x t — 4 x t — WE2 EIM_BCLK Low Level Width 0.4 x t — 0.8 x t — 1.2 x t — 1.6 x t — WE3 EIM_BCLK High Level Width 0.4 x t — 0.8 x t — 1.2 x t — 1.6 x t — WE4 Clock rise to address valid3 -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 WE5 Clock rise to address invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 WE6 Clock rise to EIM_CSx_B valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 WE7 Clock rise to EIM_CSx_B invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 WE8 Clock rise to EIM_WE_B Valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 WE9 Clock rise to EIM_WE_B Invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 WE10 Clock rise to EIM_OE_B Valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 WE11 Clock rise to EIM_OE_B Invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 WE12 Clock rise to EIM_EBx_B Valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 WE13 Clock rise to EIM_EBx_B Invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 WE14 Clock rise to EIM_LBA_B Valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 WE15 Clock rise to EIM_LBA_B Invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 WE16 Clock rise to Output Data Valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 WE17 Clock rise to Output Data Invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 WE18 Input Data setup time to Clock rise 2 — 4 — — — — — WE19 Input Data hold time from Clock rise 2 — 2 — — — — — WE20 EIM_WAIT_B setup time to Clock rise 2 — 4 — — — — — WE21 EIM_WAIT_B hold time from Clock rise 2 — 2 — — — — — |
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