IMX7DCEC datasheet(37/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to guarantee the reliable operation of the device. Any deviation

from these sequences may result in the following situations:

• Excessive current during power-up phase

• Prevention of the device from booting

Table 24. PCIe PHY reference clock Receive requirements

Description

Symbol

Interface

Speed

Min Typ Max Unit

Frequency of RBC

FRBC

20-bit

1.5 Gbps

—

MHz

3.0 Gbps

—

150

—

6.0 Gbps

—

300

—

40-bit

1.5 Gbps

—

37.5

—

3.0 Gbps

—

6.0 Gbps

—

150

—

Duty cycle of TBC

DCRBC

—

RXD[0:30] delay time from the falling edge of RBC

TDLY,RX

—

1.33

Latency from the leading edge of the corresponding first

received serial input bit, RXP/RXN, to the rising edge of RBC

TLAT.RX

20-bit

1.5 Gbps

—

100

—

bits

2.5 Gbps

—

230

—

3.0 Gbps

—

100

—

5.0 Gbps

—

260

—

6.0 Gbps

—

100

—

Table 25. PCIe PHY output clock characteristics

Description

Symbol

Interface

Speed

Min

Typ

Max

Unit

Frequency of PC_CLK

FPC_CLK

HIGH_SPEED=1

MHz

PCIe

—

250

—

Duty Cycle of PC_CLK

DCPC_CLK

—

Frequency of TX_CLK

FTX_CLK

20-bit

1.5 Gbps

—

MHz

3.0 Gbps

—

150

—

6.0 Gbps

—

300

—

40-bit

1.5 Gbps

—

37.5

—

3.0 Gbps

—

6.0 Gbps

—

150

—

Duty cycle of TX_CLK

DCTX_CLK

—

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