IMX7DCEC datasheet(28/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

4.1.6

Power modes

The i.MX 7Dual has the following power modes:

• OFF mode: all power rails are off

• SNVS mode: only RTC and tamper detection logic is active

• LPSR mode: an extension of SNVS mode, with 16 GPIOs in low power state retention mode

• RUN Mode: all external power rails are on, CPU is active and running, other internal module can

be on/off based on application;

• Low Power mode (System Idle, Low Power Idle, and Deep Sleep): most external power rails are

still on, CPU is in WFI state or power gated, most of the internal modules are clock gated or power

gated

DRAM_VREF

From PMIC

—

NVCC_DRAM_CKE

From PMIC

—

NVCC_DRAM

From PMIC

—

—3

1 The actual maximum current drawn from VDDA_1P8_IN is as shown plus any additional current drawn from the

VDDD_1P0_CAP, VDD_1P2_CAP, VDDA_PHY_1P8 outputs, depending on actual application configuration (for example,

VDD_MIPI_1P0, VDD_USB_H_1P2 and PCIE_VP/VPH supplies).

2 General equation for estimated, maximal power consumption of an I/O power supply:

Imax = N  C  V  (0.5  F)

where:

N = Number of I/O pins supplied by the power line

C = Equivalent external capacitive load

V = IO voltage

(0.5  F) = Data change rate, up to 0.5 of the clock rate (F)

In this equation, Imax is in amps, C in farads, V in volts, and F in hertz.

3 The DRAM power consumption is dependent on several factors, such as external signal termination. DRAM power calculators

are typically available from the memory vendors. They take into account factors such as signal termination. See the application

note, i.MX 7DS Power Consumption Measurement (AN5383) for examples of DRAM power consumption during specific use

case scenarios.

Table 12. Maximum supply currents(continued)

Power Rail

Source

Conditions

Max Current

Unit

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