IMX7DCEC datasheet(46/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

4.5.3

Differential I/O port (CCM_CLK1P/N)

The clock I/O interface is designed to be compatible with TIA/EIA 644-A standard. See TIA/EIA

STANDARD 644-A, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface

Circuits (2001), for details.

Table 34 shows the clock I/O DC parameters.

DC High-Level input voltage

Vih_DC

—

VRef + 0.100

OVDD

DC Low-Level input voltage

Vil_DC

—

OVSS

VRef – 0.100

Differential Input Logic High

Vih_diff

—

0.26

See note1

—

Differential Input Logic Low

Vil_diff

—

See note1

-0.26

—

Pull-up/Pull-down Impedance Mismatch

Mmpupd

—

–15

240 ?unit calibration resolution

Rres

—

Keeper Circuit Resistance

Rkeep

—

110

175

Input current (no pull-up/down)

Iin

VI = 0, VI = OVDD

-2.5

2.5



1 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

Table 34. Differential clock I/O DC electrical characteristics

Symbol

Parameter

Test conditions

Min

Typ Max Unit

Notes

Vod

Output Differential Voltage

Rload=100  between padp

and padn

250

350

450 mV Vpadp–Vpadn

Voh

High-level output voltage

1.025 1.175 1.325 V 1

Vol

Low-level output voltage

0.675 0.825 0.975

Vocm

Output common mode voltage

0.9

1.1

Core supply is used

Vid

Input Differential Voltage

100

600 mV Vpadp–Vpadn

Vicm

Input common mode voltage

50m

1.57

V Vicm(max)=ovdd(m

in)–Vid(min)/2

Icc-ovdd

Tri-state I/O supply current

ipp_ibe=ipp_obe=0 irefin

disabled (0uA)

0.46 uA

Table 33. LPDDR3 I/O DC electrical parameters(continued)

Parameters

Symbol

Test

Conditions

Min

Max

Unit

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