IMX7DCEC datasheet(85/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

4.10.2.2 eMMC4.4/4.41 (dual data rate) AC timing

Figure 47 depicts the timing of eMMC4.4/4.41. Table 62 lists the eMMC4.4/4.41 timing characteristics.

Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).

Figure 47. eMMC4.4/4.41 timing

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD7

uSDHC Input Setup Time

tISU

2.5

—

SD8

uSDHC Input Hold Time4

tIH

1.5

—

1 In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

2 In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0

–25 MHz. In High-speed mode,

clock frequency can be any value between 0

–50 MHz.

3 In Normal (Full) -Speed mode for MMC card, clock frequency can be any value between 0

–20 MHz. In High-speed mode,

clock frequency can be any value between 0

–52 MHz.

4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

Table 62. eMMC4.4/4.41 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (eMMC4.4/4.41 DDR)

fPP

MHz

SD1

Clock Frequency (SD3.0 DDR)

fPP

MHz

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD2

uSDHC Output Delay

tOD

2.7

6.9

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

Table 61. SD/eMMC4.3 interface timing specification(continued)

Parameter

Symbols

Min

Max

Unit

SD1

SD2

SD3

Output from eSDHCv3 to card

Input from card to eSDHCv3

SDx_DATA[7:0]

SDx_CLK

SD4

SD2

......

SDx_DATA[7:0]

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