LTC7813 datasheet(34/59 Pages) AD

34 / 59 page

Data Sheet

LT8210-1

analog.com

Rev. A

34 of 59

Multiple LT8210-1 can share common resistor dividers for the FB1 and FB2 inputs, although routing these noise

sensitive signals between phases can affect stability. Alternatively, each phase can use its own FB1 and FB2 dividers

at the expense of less accurate current sharing. This can be mitigated by using 0.1% tolerance resistors for the

feedback dividers.

Buck Foldback

The LT8210-1 actively prevents inductor current runaway while the buck loop is switching. The inductor current can

run away when its rising slope exceeds the falling slope to such a degree that the current continues to increase each

period even while switching at the minimum SW1 duty cycle. A buck regulator is most susceptible to runaway when

the output voltage is near ground, causing the inductor current falling slope to be flat. This situation is exacerbated

by a high input voltage and a high switching frequency. To prevent runaway, the LT8210-1 may skip switch A pulses

while VOUT is less than 10% of VINP and the FB1 voltage is lower than 900mV. At the start of the switch A on-time, the

sensed inductor current must be below an internally set pulse-skipping threshold; otherwise, the next pulse on

switch A will be skipped. If the inductor current exceeds the pulse-skipping threshold on the next switch A turn-on,

the following three pulses will be skipped, and so on. The foldback circuit increases the number of skipped pulses

with each successive switch A pulse where this threshold is exceeded; otherwise, the skip count is reset. In addition

to preventing inductor runaway, the LT8210-1 foldback scheme significantly reduces switch A power dissipation in a

short circuit condition. When the output is shorted to ground, the power dissipation in switch A is dominated by

transitional losses as it turns on and off. Reducing the number of switch A pulses over a given period reduces the

dissipated power proportionally. The boost loop is naturally protected from inductor current runaway in the LT8210-

1 as it can only occur when VINP ~ VOUT, which is within the buck-boost region. While the buck loop is simultaneously

controlling the inductor current each cycle, it is not possible for the boost channel to run away.

PWGD Pin

The PWGD pin is an open drain logic output that goes high when the output voltage and IMON pin voltage are within

preset limits after switching is enabled. The internal PWGD pull-down is released when VOUT is within ±10% of its

programmed value. In CCM and DCM operations, this occurs when the FB1 voltage is within ±10% of the 1.00V

reference. In pass-thru mode, PWGD will go high when VFB1> 0.90V and VFB2 < 1.10V, indicating that the output voltage

is within ±10% of the programmed output pass-thru window. PWGD will be pulled low if the voltage on the IMON pin

exceeds 1.20V, indicating that the average current exceeds its programmed limit by 20% or more. The LT8210-1

includes a built-in self-test to confirm the system reference circuitry is functioning properly. This reference voltage

is used for voltage regulation, current regulation, clock generation, and fault detection. If the system reference is

outside of preset tolerances, switching is disabled, and the PWGD pin is pulled low. Switching will also be disabled,

and the PWGD pin will be pulled low if the VINP, GATEVCC, VDD, or DG pin voltages fall below their respective

undervoltage lockout thresholds. The PWGD pin pull-up resistor can be connected to any external rail up to 40V.

Using either VDD or GATEVCC as the pull-up supply has the added advantage that PWGD will be in the correct state

when the LT8210-1 is disabled. Figure 59 shows the conditions that determine the state of the PWGD pin.

LTC7813 Datasheet(PDF) 34 Page - Analog Devices