SAA7780 datasheet(46/70 Pages) PHILIPS

46 / 70 page

ThunderBird Q3D PCI Audio

SAA7780

Accelerator

Philips Semiconductors

Product Specification

1999 Sep 30

Miscellaneous Configuration Register - MSCCFG (RO/RW)

PCI Configuration Space 1

The following table is a summary of all the PCI configuration space registers. The registers that are block-mates with

the PCI interface (offset 00h - 3Ch) will be detailed following this table. The remainder of the registers will be detailed

with the blocks they control. This register space is for the joystick.

PCI Configuration Space 1 Register Map

PCI CFG 0

Offset 58h

ASYMCLK[1:0]

RDY_EN

CFGCLK

BHEN

PCCH[1:0]

PCPCI

_EN

POR Value

Bit

Name

R/W

Function

7:6

ASYMCLK

Asymmetrical Clock Select. These bits program the duty cycle for the input

for the two phase DSP clock generator.

RDY_EN

Music registers ready enable. When set, the music registers will cause the

PCI interface to retry when either of the music registers (music0 or music1)

are full.

CFGCLK

Serial Configuration Port Clock Select. This bit selects the clock output to the

Configuration Serial Port.

0 = Ouput a 400 KHz clock. Incoming data will be synchronized to this clock.

1 = Output the PCI clock.

BHEN

Bus Hog Fix Enable.

2:1

PCCH

These two bits are the encoded channel number that the soundblaster will be

on in the PC/PCI mode and are valid only when the PC/PCI mode is enabled.

PCPCI_EN

PC/PCI mode enable bit. This bit, when set = 1, will enable the PC/PCI

sideband signals for the Soundblaster legacy mode.

Byte 3

Byte 2

Byte 1

Byte 0

Offset

Device ID

Vendor ID

00h

Status

Command

04h

Class Code

Revision ID

08h

BIST

Header Type

Master Latency Timer

Cache Line Size

0Ch

GMBASE

10h

Reserved

14-2B

Subsystem ID

Subsystem Vendor ID

2Ch

Reserved

30-3Bh

Max_Lat

Min_Gnt

Interrupt Pin

Interrupt Line

3Ch

Reserved

40-6Bh

Reserved

GAMECFG0

6Ch

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