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SAA7780 Datasheet(PDF) 54 Page - NXP Semiconductors |
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SAA7780 Datasheet(HTML) 54 Page - NXP Semiconductors |
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54 / 70 page ![]() ThunderBird Q3D PCI Audio SAA7780 Accelerator Philips Semiconductors Product Specification 1999 Sep 30 54 Interrupt PIN Register - INTPIN (RO) MIN_GNT Register - MINGNT (RO) MAX_LAT Register - MAXLAT (RO) Bit Name R/W Function 7:0 INTLINE RO Interrupt Line. The Interrupt Line register is an eight bit register used to communicate interrupt line routing information. The value in this register tells which input of the system interrupt controller(s) the SAA7780 Device's interrupt pin is connected to. It is set to 00h to use function 0’s interrupt line. There is no legacy interrupt support for function 1. PCI CFG 1 D7 D6 D5 D4 D3 D2 D1 D0 Offset 3Dh INTPIN[7:0] POR Value 0 0 0 0 0 0 0 0 Bit Name R/W Function 7:0 INTPIN RO Interrupt Pin. The interrupt pin register tells which interrupt the SAA7780 device uses. The read only value of 00h implies that the SAA7780 device shares the INT A interrupt pin with function 0. There is no legacy interrupt support for function 1. PCI CFG 1 D7 D6 D5 D4 D3 D2 D1 D0 Offset 3Eh MINGNT[7:0] POR Value 0 0 0 0 0 0 0 0 Bit Name R/W Function 7:0 MINGNT RO Minimum grant specifies how long of a burst period the device needs assuming a clock speed of 33MHz. Since the SAA7780, function 1, is a target only, this register is read only and set to zero. PCI CFG 1 D7 D6 D5 D4 D3 D2 D1 D0 Offset 3Fh MAXLAT[7:0] POR Value 0 0 0 0 0 0 0 0 |
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