SAA7780 datasheet(37/70 Pages) PHILIPS

37 / 70 page

ThunderBird Q3D PCI Audio

SAA7780

Accelerator

Philips Semiconductors

Product Specification

1999 Sep 30

Master Latency Timer Register - Latime (RW)

Header Type Register - Header (RO)

BIST Register - BIST (RO)

Bit

Name

R/W

Function

7:0

CACHELINE

Reserved for cache line size indicator.

PCI CFG 0

Offset 0Dh

LATIME[7:0]

POR Value

Bit

Name

R/W

Function

7:0

LATIME

The primary bus latency timer specifies the number of primary clocks that the

primary master may consume. The timer is reloaded at each assertion of

FRAME# by the primary master. If the primary master loses its bus grant,

then it must relinquish the bus after the timer expires.

PCI CFG 0

Offset 0Eh

MULTI_

HEADER[6:0]

POR Value

Bit

Name

R/W

Function

MULTI_FN

A 1 indicates that the SAA7780 is a multi-function device. The three PCI

configuration headers are accessed by the configuration cycle address bits

10-8. The function definitions are as follows:

0 = Audio Subsystem

1 = Joystick

2 = 16650 UART

6:0

HEADER

Header Type. A 00h indicates this device is a not a PCI-to-PCI bridge.

PCI CFG 0

Offset 0Fh

BIST

START

CODE[3:0]

POR Value

SAA7780 Datasheet(PDF) 37 Page - NXP Semiconductors

SAA7780 Datasheet(HTML) 37 Page - NXP Semiconductors

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