SAA7780 datasheet(23/70 Pages) PHILIPS

23 / 70 page

ThunderBird Q3D PCI Audio

SAA7780

Accelerator

Philips Semiconductors

Product Specification

1999 Sep 30

AC’97 CODEC Interface

MD[15:0]

103,105,106,

107,108,109,

110,111,113,

114,115,116,

118,119,122,

123

IO-T

External Memory Data Bus

Word wide data bus for the external SRAM. Use 6ns memory for

DSP code usage and 20 ns memory for reverb usage.

MCS#

144

O-T

External Memory Chip Select

Chip select line for the external SRAM devices.

MWE#

133

O-T

External Memory Read/Write Control

Selects the external SRAM for reading or writing.

SYNC

O-T

AC’97 Codec Synchronization/Frame Output

This signal is used to frame the tag packet from the AC link designer

from the SAA7780 chip.

BIT_CLK

AC’97 Data Bit Clock

This signal is used to clock synchronous data on the AC link

interface.

SDATA_OUT

O-T

AC’97 Serial Data Out

This is the time division multiplexed serial output data stream from

the SAA7780 controller.

SDATA_IN

AC’97 Serial Data In

This is the time division multiplexed serial input data stream the

external AC’97 codec.

AC_RST_N#

O-T

AC’97 Master Reset

The external AC’97 codec has a master reset line which is has a

separate control. The codec status must report a ready before any

audio or modem data is transmitted to the codec.

SAA7780 Datasheet(PDF) 23 Page - NXP Semiconductors

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