SAA7780 datasheet(25/70 Pages) PHILIPS

25 / 70 page

ThunderBird Q3D PCI Audio

SAA7780

Accelerator

Philips Semiconductors

Product Specification

1999 Sep 30

Legend:

CMOS-compatible input

AGND

Analog ground

DGND

Digital ground pin

Input-only pin (can become bidirectional for test mode)

Bidirectional pin

Output-only pin (can become bidirectional for test mode)

APWR

Analog power supply pin

DPWR

Digital power supply pin

TTL-compatible input

Indicates a high-impedance with approximately 10 K¾ minimum resistance to VSS (internal pull-down

resistor on pin)

Indicates a high-impedance with approximately 10 K¾ minimum resistance to VDD (internal pull-up resis-

tor on pin)

PUB

Inidcates that this pin needs an external pull-up resistor when the chip is installed on a board or tester. A

10K ohm resistor is nominal

Indicates a Schmitt-trigger input with hysteresis for noise immunity

Three-state pin

STS

Sustained three-state output / TTL input (if applicable)

Open drain pad

Analog based I/O. Use a pad with ESD protection

Core power. Denotes a pad that supplies power for the core of the chip only

Core ground. Denotes a pad that supplies ground to the core only

Ring power. Denotes a pad that supplies power to the pads only

Ring ground. Denotes a pad that supplies ground to the ring only

RPD

Ring power with option to power core level shifter. Denotes a pad that supplies power to the ring while its

core side connector can optionally supply internal level shifters

RCG

Ring/core ground. Denotes a pad that supple a ground connection to the ring and core

High impedance. When in a three state test mode, this pin will be forced into a high impedance state

Nand tree. When in a NAND tree test mode, this pin will be included in the parametric NAND tree logic

NTO

Nand tree output. When in a NAND tree test mode, this pin is the output of the parametric NAND tree

FSB

Function System Block test. Denotes that his pin is not timing critical and is available for FSB multiplexing

VDD

1,142,28,41,

54,68,80,96,

112,121,135,

142

DPWR

Ring Power

VWELL

117

DPWR

External N-Well Bias

Tie these pins to 5V for proper 5 volt tolerant operation. The 5V

supply must be powered up before the 3V supply. Likewise, the 3V

supply must be powered down before the 5V supply.

SAA7780 Datasheet(PDF) 25 Page - NXP Semiconductors

SAA7780 Datasheet(HTML) 25 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL