SST85LD0128 datasheet(28/73 Pages) SST

28 / 73 page

Advance Information

NANDrive

SST85LD0128 / SST85LD0256 / SST85LD0512

S71319-03-000

2/07

12.2.1.6.23 Word 66: Device Recommended Multi-word DMA Cycle Time

This field defines the NANDrive recommended Multi-word DMA transfer cycle time. This field defines, in

nanoseconds, the minimum cycle time per word during a single sector host transfer while performing a

multiple sector READ DMA or WRITE DMA command for any location on the media under nominal

conditions. If a host runs at a faster cycle rate by operating at a cycle time of less than this value, the

NANDrive may negate DMARQ for flow control. The rate at which DMARQ is negated could result in

reduced throughput despite the faster cycle rate. Transfer at this rate does not ensure that flow control

will not be used, but implies that higher performance may result. SST NANDrive supports up to Multi-

word DMA Mode-2, so this field is set to 120 ns.

12.2.1.6.24 Word 67: Minimum PIO Transfer Cycle Time Without Flow Control

The NANDrive’s minimum cycle time is 120 ns.

12.2.1.6.25 Word 68: Minimum PIO Transfer Cycle Time With IORDY

The NANDrive’s minimum cycle time is 120 ns, e.g., PIO Mode-4.

12.2.1.6.26 Word 80: Major Version Number

If not 0000H or FFFFH, the device claims compliance with the major version(s) as indicated by bits (6:1)

being set to one. Since ATA standards maintain downward compatibility, a device may set more than

one bit. NANDrive supports ATA-1 to ATA-6.

12.2.1.6.27 Word 81: Minor Version Number

If an implementer claims that the revision of the standard they used to guide their implementation does

not need to be reported or if the implementation was based upon a standard prior to the ATA-3

standard, word 81 should be 0000H or FFFFH.

A value of 0019H reported in word 81 indicates ATA/ATAPI-6 T13 1410D revision 3a guided the

implementation.

SST85LD0128 Datasheet(PDF) 28 Page - Silicon Storage Technology, Inc