SST85LD0128 datasheet(65/73 Pages) SST

65 / 73 page

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SST85LD0128 / SST85LD0256 / SST85LD0512

S71319-03-000

2/07

13.2.3 Multi-word DMA Data Transfer

Note: All AC specifications are guaranteed by design.

FIGURE

13-4: Initiating a Multi-word DMA Data Transfer

TABLE

13-9: Multi-word DMA Timing Parameters - Mode 2

Symbol

Parameter

Min

Max

Units

T01

1. T0 is the minimum total cycle time, TD is the minimum IORD#/IOWD# assertion time, and TK (TKR or TKW, as appropriate)

is the minimum IORD#/IOWD# negation time. A host should lengthen TD and/or TK to ensure that T0 is equal to the value

reported in the device ID.

Cycle Time

120

IORD#/IOWD# Asserted Pulse Width

IORD# Data Access

IORD# Data Hold

IORD#/IOWD# Data Setup

IOWD# Data Hold

DMACK# to IORD#/IOWR# Setup

IORD#/IOWD# to DMACK Hold

TKR

IORD# Negated Pulse Width

TKW

IOWD# Negated Pulse Width

TLR

IORD# to DMARQ Delay

TLW

IOWD# to DMARQ Delay

CS(1:0) Valid to IORD#/IOWD#

CS(1:0) Hold

DMACK# to Read Data Released

T13-9.0 1319

Note:

The host should not assert DMACK# or negate both CS1FX#

and CS3FX# until the assertion of DMARQ is detected.

The maximum time from the assertion of DMARQ to the assertion

of DMACK# or the negation of both CS0 and CS1 is not defined.

Write DQ15-0

Read DQ15-0

IORD#/IOWR

DMACK#

DMARQ

CS1FX#/CS3FX#

1319 F05.0

See note

SST85LD0128 Datasheet(PDF) 65 Page - Silicon Storage Technology, Inc

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