H838024 datasheet(348/697 Pages) RENESAS

348 / 697 page

Section 9 Timers

Rev. 7.00 Mar 10, 2005 page 306 of 652

REJ09B0042-0700

Timer Counter W (TCW)

Bit

Initial value

Read/Write

TCW7

R/W

TCW6

R/W

TCW5

R/W

TCW4

R/W

TCW3

R/W

TCW0

R/W

TCW2

R/W

TCW1

R/W

For the H8/38024, H8/38024S, and H8/38024R groups, the clock source is

φ/8,192 or φw/32. For

the H8/38124 group, the clock source is selected based on the timer mode register (TMW) setting

if WDCKS is 0 and is

φw/32 if WDCKS is 1.

When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to

1 in TCSRW. Upon reset, TCW is initialized to H'00.

Timer Mode Register (TMW)

Bit

—

CKS3

CKS2

CKS1

CKS0

Initial value

Read/Write

—

R/W

The TMW register is only implemented on the H8/38124. The input clock is selected using

combinations of CKS3 to CKS0.

Bits 7 to 4—Reserved

These bits are always read as 1.

Bits 3 to 0—Clock Select (CKS3 to CKS0)

These bits are used to select the clock input to TCW from among 10 internal options. Clock source

selection using this register is enabled when WDCKS in port mode register 2 (PMR2) is cleared to

0. If WDCKS is set to 1 the

φw/32 clock source is selected, regardless of the settings of the bits in

this register.

H838024 Datasheet(PDF) 348 Page - Renesas Technology Corp

H838024 Datasheet(HTML) 348 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL