H838024 datasheet(349/697 Pages) RENESAS

349 / 697 page

Section 9 Timers

Rev. 7.00 Mar 10, 2005 page 307 of 652

REJ09B0042-0700

Bit 3

CKS3

Bit 2

CKS2

Bit 1

CKS1

Bit 0

CKS0

Description

1000Internal clock:

φ/64 count

Internal clock:

φ/128 count

Internal clock:

φ/256 count

Internal clock:

φ/512 count

100Internal clock:

φ/1024 count

Internal clock:

φ/2048 count

Internal clock:

φ/4096 count

Internal clock:

φ/8192 count

(initial value)

XXXWatchdog on-chip oscillator

Note:

X: Don't care

Clock Stop Register 2 (CKSTPR2)

LVDCKSTD*

WDCKSTP PW1CKSTP LDCKSTP



PW2CKSTP AECKSTP

6543210

1111111

R/W



R/W

Bit

Initial value

Read/Write

Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group.

CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral

modules. Only the bit relating to the watchdog timer is described here. For details of the other

bits, see the sections on the relevant modules.

Bit 2—Watchdog Timer Module Standby Mode Control (WDCKSTP)

Bit 2 controls setting and clearing of module standby mode for the watchdog timer.

WDCKSTP

Description

Watchdog timer is set to module standby mode

Watchdog timer module standby mode is cleared

(initial value)

Note:

WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W

(TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer

operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog

function and will not enter module standby mode. When the watchdog function ends and

WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the

watchdog timer will enter module standby mode.

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