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H838024 Datasheet(PDF) 360 Page - Renesas Technology Corp |
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H838024 Datasheet(HTML) 360 Page - Renesas Technology Corp |
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360 / 697 page  Section 9 Timers Rev. 7.00 Mar 10, 2005 page 318 of 652 REJ09B0042-0700 Bits 5 and 4—AEC Clock Select L (ACKL1, ACKL0) Bits 5 and 4 select the clock used by ECL. Bit 5 ACKL1 Bit 4 ACKL0 Description 0 0 AEVL pin input (initial value) 1 φ/2 10 φ/4 1 φ/8 Bits 3 to 1—Event Counter PWM Clock Select (PWCK2, PWCK1, PWCK0) Bits 3 to 1 select the event counter PWM clock. Bit 3 PWCK2 Bit 2 PWCK1 Bit 1 PWCK0 Description 000 φ/2 (initial value) 1 φ/4 10 φ/8 1 φ/16 1 * 0 φ/32 1 φ/64 *: Don’t care Bit 0—Reserved Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset. Note: Do not set this bit to 1. |
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