H838024 datasheet(362/697 Pages) RENESAS

362 / 697 page

Section 9 Timers

Rev. 7.00 Mar 10, 2005 page 320 of 652

REJ09B0042-0700

Bit 6

OVL

Description

ECL has not overflowed

(initial value)

Clearing condition:

After reading OVL = 1, cleared by writing 0 to OVL

ECL has overflowed

Setting condition:

Set when ECL overflows from H'FF to H'00

Bit 5—Reserved

Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.

Bit 4—Channel Select (CH2)

Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two

independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a

16-bit event counter which is incremented each time an event clock is input to the AEVL pin. In

this case, the overflow signal from ECL is selected as the ECH input clock. When CH2 is set to 1,

ECH and ECL function as independent 8-bit event counters which are incremented each time an

event clock is input to the AEVH or AEVL pin, respectively.

Bit 4

CH2

Description

ECH and ECL are used together as a single-channel 16-bit event counter

(initial value)

ECH and ECL are used as two independent 8-bit event counter channels

Bit 3—Count-up Enable H (CUEH)

Bit 3 enables event clock input to ECH. When 1 is written to this bit, event clock input is enabled

and increments the counter. When 0 is written to this bit, event clock input is disabled and the

ECH value is held. The AEVH pin or the ECL overflow signal can be selected as the event clock

source by bit CH2.

Bit 3

CUEH

Description

ECH event clock input is disabled

(initial value)

ECH value is held

ECH event clock input is enabled

H838024 Datasheet(PDF) 362 Page - Renesas Technology Corp