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H838024 Datasheet(PDF) 205 Page - Renesas Technology Corp |
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H838024 Datasheet(HTML) 205 Page - Renesas Technology Corp |
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205 / 697 page  Section 6 ROM Rev. 7.00 Mar 10, 2005 page 163 of 652 REJ09B0042-0700 Bit 7—Power-down Disable (PDWND) This bit selects the power-down mode of the flash memory when a transition to the subactive mode is made. Bit 7 PDWND Description 0 When this bit is 0 and a transition is made to the subactive mode, the flash memory enters the power-down mode. (initial value) 1 When this bit is 1, the flash memory remains in the normal mode even after a transition is made to the subactive mode. Bits 6 to 0—Reserved These bits are always read as 0 and cannot be modified. 6.6.5 Flash Memory Enable Register (FENR) Bit 7 654 321 0 FLSHE ——— ——— — Initial value 0 0 0 0 0 0 0 0 Read/Write R/W — — — — — — — FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and FLPWCR. Bit 7—Flash Memory Control Register Enable (FLSHE) This bit controls access to the flash memory control registers. Bit 7 FLSHE Description 0 Flash memory control registers cannot be accessed (initial value) 1 Flash memory control registers can be accessed Bits 6 to 0—Reserved These bits are always read as 0 and cannot be modified. |
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