H838024 datasheet(299/697 Pages) RENESAS

299 / 697 page

Section 9 Timers

Rev. 7.00 Mar 10, 2005 page 257 of 652

REJ09B0042-0700

Timer Counter C (TCC)

Bit

Initial value

Read/Write

TCC7

TCC6

TCC5

TCC4

TCC3

TCC0

TCC2

TCC1

TCC is an 8-bit read-only up/down-counter, which is incremented or decremented by internal

clock or external event input. The clock source for input to this counter is selected by bits TMC2

to TMC0 in timer mode register C (TMC). TCC values can be read by the CPU at any time.

When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to

H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1.

TCC is allocated to the same address as TLC.

Upon reset, TCC is initialized to H'00.

Timer Load Register C (TLC)

Bit

Initial value

Read/Write

TLC7

TLC6

TLC5

TLC4

TLC3

TLC0

TLC2

TLC1

TLC is an 8-bit write-only register for setting the reload value of timer counter C (TCC).

When a reload value is set in TLC, the same value is loaded into timer counter C as well, and TCC

starts counting up/down from that value. When TCC overflows or underflows during operation in

auto-reload mode, the TLC value is loaded into TCC. Accordingly, overflow/underflow period

can be set within the range of 1 to 256 input clocks.

The same address is allocated to TLC as to TCC.

Upon reset, TLC is initialized to H'00.

H838024 Datasheet(PDF) 299 Page - Renesas Technology Corp