PM5366 datasheet(125/267 Pages) PMC

125 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

113

Flexible Bandwidth Port may be output. The SBI Bus Data Formats section

provides the details of the mapping formats.

Links inserted into the SBI bus can be synchronous to the SBI bus (by setting

SYNCH_TRIB=1 in the INSBI Control RAM) or timed from the upstream data

source via the sonet/sdh mapper, M13, or DS3/E3 framer. When SYNCH_TRIB

is logic 0, the INSBI makes link rate adjustments by adding or deleting an extra

byte of data over a 500

µS interval based on buffer fill levels. Timing

adjustments are detected by the receiving SBI interface by explicit signals in the

SBI bus structure. When SYNCH_TRIB is logic 1, the tributary is “locked” in

which no timing adjustments are allowed. The frame slip buffer (ELST) must be

in the datapath in “locked” mode.

The INSBI always sends valid link rate information across the SBI Drop bus,

which contains both ClkRate(1:0) and Phase(3:0) field information. this gives an

external device receiving data from the INSBI three methods of creating a

recovered link clock: the ClkRate field, the Phase field, or just the rate of data

flow across the SBI drop bus. INSBI does not generate the Phase field for

DS3/E3 tribs.

For byte synchronous mapping applications, channelized T1s inserted into the

SBI bus optionally have the channel associated signaling (CAS) bits explicitly

defined and carried in parallel with the DS0s or timeslots.

9.35 Flexible Bandwidth Ports

Three Flexible Bandwidth Ports are provided to supply arbitary bandwidth signals

to the SBI bus. Each port is associated with one SPE on the SBI bus and may

carry up to the capacity of the SPE (49.5 Mbit/s).

In the ingress direction, data is presented as a three wire interface: a clock of up

to 51.84 MHz, bit serial data and an enable. No flow control is provided, so the

average data rate must be less than 49.5 Mbit/s.

In the egress direction, a simple handshake controls the data flow. For each

cycle that the EFBWDREQ[n] input is high, a bit may be output on the

EFBWDAT[n] output. The data is supplied from the SBI bus FIFO, which will be

kept half full through the SAJUST_REQ asserts as required.

9.36 JTAG Test Access Port

The JTAG Test Access Port block provides JTAG support for boundary scan.

The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST

PM5366 Datasheet(PDF) 125 Page - PMC-Sierra, Inc

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