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PM7326 Datasheet(PDF) 21 Page - PMC-Sierra, Inc |
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PM7326 Datasheet(HTML) 21 Page - PMC-Sierra, Inc |
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21 / 238 page ![]() PM7326 S/UNI APEX DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 5 • Microprocessor port to any loop or WAN port. • Any loop or WAN port to microprocessor port • VP Termination (in conjunction with ATLAS) • VPI or VPI/VCI header mapping • VC merge • Provides flexible signaling and control capabilities • Provides 4 independent uP transmit queues • Provides simultaneous AAL5 SAR assistance for traffic to/from the uP on up to 64k VCs. • Supports uP cell injection into any queue. • Provides per VC selectable OAM cell pass through or switching to microprocessor port. • Supports CRC10 calculation for OAM cells destined for/originating from the microprocessor. • Diagnostic access provided to context memory and cell buffer memory via the microprocessor. • Provides per VC CLP0/1 transmit counts. • Provide global per CLP0/1 discard counts • Provides various error statistics accumulation. • Determines the ingress connection identifier from one of several locations: the cell prepend, the VPI/VCI field, or the HEC/UDF field. • Interface support • Provides a 8/16-bit Any-PHY compliant master/slave Loop side interface supporting up to 2048 ports (logical PHYs). • Provides an 8/16-bit Any-PHY compliant master/slave WAN side interface supporting up to 4 ports (PHYs). |
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