PM7326 datasheet(41/238 Pages) PMC

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PM7326 S/UNI APEX

DATA SHEET

PMC-1981224

ISSUE 6

ATM/PACKET TRAFFIC MANAGER AND SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin Name

Type

No.

Function

LTSX

Output

U25

Loop Transmit Start of Transfer. LTSX is asserted

by the S/UNI APEX during the first cycle of a data

block transfer. LTSX assertion will coincide with the

port address prepend, if the cell being transferred

has a prepended port address. Required only

during Any-PHY mode. Should be left unconnected

during UTOPIA modes.

LTSX is updated on the rising edge of LTCLK.

LTSOP

Output

(Master)

Tri-state

(Slave)

T23

Loop Transmit Start of Cell. LTSOP marks the

start of cell on the LTDAT[15:0] data bus. LTSOP is

driven high when the first word of the cell (excluding

address prepend) is present on the LTDAT[15:0]

stream. LTSOP is asserted for each cell.

In transmit master mode, the signal is always

driven.

In receive slave mode, this signal is driven 1 LTCLK

after LTENB is asserted.

LTSOP is updated/Hi-Z’d on the rising edge of

LTCLK.

LTDAT[0]

LTDAT[15]

Output

(Master)

Tri-state

(Slave)

T26

R24

R25

R26

P24

P25

N25

N24

N23

M26

M25

M24

L26

M23

L25

L24

Loop Transmit Data. LTDAT[15:0] carries the data

block transfers to the physical layer devices.

In 8 bit mode, only LTDAT[7:0] are valid.

In transmit master mode, the entire bus is always

driven.

In receive slave mode, this bus is driven 1 LTCLK

after LTENB is asserted. Pull up/downs are

required for the entire bus, regardless of whether

the bus is in 8 or 16 bit mode.

LTDAT[15:0] is updated/Hi-Z’d on the rising edge of

LTCLK.

PM7326 Datasheet(PDF) 41 Page - PMC-Sierra, Inc

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