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AM69 Datasheet(PDF) 117 Page - Texas Instruments |
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AM69 Datasheet(HTML) 117 Page - Texas Instruments |
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117 / 312 page  Table 5-85. PCIE Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] AND PIN [4] PCIE3_TXN1 O SERDES_PCIE Differential Transmit Data (negative) AV12 AK18 PCIE3_TXP0 O SERDES_PCIE Differential Transmit Data (positive) AV10 AM15 PCIE3_TXP1 O SERDES_PCIE Differential Transmit Data (positive) AV13 AK17 PCIE_REFCLK0_N_OUT O SERDES_PCIE Reference Clock Negative AP4 AJ13 PCIE_REFCLK0_P_OUT O SERDES_PCIE Reference Clock Positive AP5 AJ12 PCIE_REFCLK1_N_OUT O SERDES_PCIE Reference Clock Out Negative AN8 AH14 PCIE_REFCLK1_P_OUT O SERDES_PCIE Reference Clock Out Positive AN9 AH13 PCIE_REFCLK2_N_OUT O SERDES_PCIE Reference Clock Out Negative AN5 AH11 PCIE_REFCLK2_P_OUT O SERDES_PCIE Reference Clock Out Positive AN6 AH10 PCIE_REFCLK3_N_OUT O SERDES_PCIE Reference Clock Out Negative AP7 AJ16 PCIE_REFCLK3_P_OUT O SERDES_PCIE Reference Clock Out Positive AP8 AJ15 5.3.19 SERDES 5.3.19.1 MAIN Domain Table 5-86. SERDES0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] AND PIN [4] SERDES0_REFCLK_N IO Serdes Reference Clock Input/Output (negative) AU9 AK15 SERDES0_REFCLK_P IO Serdes Reference Clock Input/Output (positive) AU8 AK14 SERDES0_REXT (1) I External Calibration Resistor AN11 AG7 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. Table 5-87. SERDES1 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] AND PIN [4] SERDES1_REFCLK_N IO Serdes Reference Clock Input/Output (negative) AV3 AN5 SERDES1_REFCLK_P IO Serdes Reference Clock Input/Output (positive) AV4 AN6 SERDES1_REXT (1) I External Calibration Resistor AL9 AH9 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. Table 5-88. SERDES2 Signal Descriptions SIGNAL NAME [1] ((2)) PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] AND PIN [4] SERDES2_REFCLK_N IO Serdes Reference Clock Input/Output (negative) AV21 SERDES2_REFCLK_P IO Serdes Reference Clock Input/Output (positive) AV22 SERDES2_REXT (1) IO External Calibration Resistor AL20 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. (2) DDRSS2, DDRSS3, and SERDES2 are not available on the 27mm package variant of this SoC. DDRSS2/DDRSS3/SERDES2 should be avoided if software compatibility is desired with systems that use the 27mm package. www.ti.com AM69A, AM69 SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 117 Product Folder Links: AM69A AM69 |
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