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AM69 Datasheet(PDF) 131 Page - Texas Instruments |
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AM69 Datasheet(HTML) 131 Page - Texas Instruments |
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131 / 312 page  Table 5-116. MCU System Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] AND PIN [4] MCU_SYSCLKOUT0 O MCU Domain system clock output for test and debug purposes only L33 B18 Table 5-117. System Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] AND PIN [4] AUDIO_EXT_REFCLK0 IO External clock routed to ATL or McASP as one of the selectable input clock sources, or as a output clock output for ATL or McASP AJ34 T30 AUDIO_EXT_REFCLK1 IO External clock routed to ATL or McASP as one of the selectable input clock sources, or as a output clock output for ATL or McASP AH37 F33 EXTINTn I External Interrupt AN35 Y29 EXT_REFCLK1 I External clock input to Main Domain, routed to Timer clock muxes as one of the selectable input clock sources for Timer/WDT modules, or as reference clock to MAIN_PLL2 (PER1 PLL) AJ32 J33 GPMC0_FCLK_MUX O GPMC functional clock output selected through a mux logic AF36 K33 OBSCLK0 O Observation clock output for test and debug purposes only AN37 W30 OBSCLK1 O Observation clock output for test and debug purposes only AG37 H32 PMIC_POWER_EN1 O Power enable output for MAIN Domain supplies L38 B16 PMIC_WAKE0n O PMIC WakeUp AJ34 T30 PMIC_WAKE1n O PMIC WakeUp M33 A20 PORz I SoC PORz Reset Signal P33 D24 RESETSTATz O Main Domain Warm Reset status output AL38 W32 RESET_REQz I Main Domain external Warm Reset request input F34 G20 SOC_SAFETY_ERRORn IO Error signal output from Main Domain ESM AM34 Y31 SYNC0_OUT O CPTS Time Stamp Generator Bit 0 AD36 L31 SYNC1_OUT O CPTS Time Stamp Generator Bit 1 AJ32 J33 SYNC2_OUT O CPTS Time Stamp Generator Bit 2 AD38 H29 SYNC3_OUT O CPTS Time Stamp Generator Bit 3 AD37 P33 SYSCLKOUT0 O SYSCLK0 output from Main PLL controller (divided by 6) for test and debug purposes only AR38 AA32 5.3.31.4 EFUSE Table 5-118. EFUSE Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] AND PIN [4] VPP_CORE PWR Programming Voltage for MAIN Domain Efuses AA31 V29 VPP_MCU PWR Programming Voltage for MCU Domain Efuses L29 F26 www.ti.com AM69A, AM69 SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 131 Product Folder Links: AM69A AM69 |
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